74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
February 2008
74VHC74
Dual D-Type Flip-Flop with Preset and Clear
Features
■
High Speed: f
MAX
=
170MHz (typ.) at T
A
=
25°C
■
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min.)
■
Power down protection is provided on all inputs
■
Low power dissipation: I
CC
=
2µA (max.) at T
A
=
25°C
■
Pin and function compatible with 74HC74
General Description
The VHC74 is an advanced high speed CMOS Dual
D-Type Flip-Flop fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar
to equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The signal level applied to
the D input is transferred to the Q output during the posi-
tive going transition of the CK pulse. CLR and PR are
independent of the CK and are accomplished by setting
the appropriate input LOW.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Order Number
74VHC74M
74VHC74SJ
74VHC74MTC
74VHC74N
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Fairchild Semiconductor Corporation
74VHC74 Rev. 1.3.0
www.fairchildsemi.com
74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
D
1
, D
2
CK
1
, CK
2
CLR
1
, CLR
2
PR
1
, PR
2
Q
1
, Q
1
, Q
2
, Q
2
Truth Table
Description
Inputs
CLR
L
H
L
H
H
H
Outputs
CK
X
X
X
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Output
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
Q
L
H
H
(1)
L
H
Q
n
Q
H
L
H
(1)
H
L
Q
n
Function
Clear
Preset
No Change
Note:
1. This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive
(HIGH) state.
©1992 Fairchild Semiconductor Corporation
74VHC74 Rev. 1.3.0
www.fairchildsemi.com
2
74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(2)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
Parameter
Rating
2.0V to +5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
Note:
2. Unused inputs must be held HIGH or LOW. They may not float.
©1992 Fairchild Semiconductor Corporation
74VHC74 Rev. 1.3.0
www.fairchildsemi.com
3
74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to
+85°C
Max.
Min.
1.50
0.7 x V
CC
0.50
0.3 x V
CC
0.50
0.3 x V
CC
1.9
2.9
4.4
2.48
3.80
V
V
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0–5.5
2.0
3.0–5.5
2.0
3.0
4.5
3.0
4.5
Conditions
Min.
1.50
0.7 x V
CC
Typ.
Max.
Units
V
V
IN
=
V
IH
or V
IL
I
OH
=
–50µA
1.9
2.9
4.4
2.0
3.0
4.5
I
OH
=
–4mA
I
OH
=
–8mA
V
IN
=
V
IH
or V
IL
I
OL
=
50µA
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
2.0
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
0.1
0.1
0.1
0.44
0.44
±1.0
20.0
V
I
OL
=
4mA
I
OL
=
8mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
I
IN
I
CC
Input Leakage
Current
Quiescent
Supply Current
0–5.5
5.5
µA
µA
©1992 Fairchild Semiconductor Corporation
74VHC74 Rev. 1.3.0
www.fairchildsemi.com
4
74VHC74 — Dual D-Type Flip-Flop with Preset and Clear
AC Electrical Characteristics
T
A
=
25°C
Symbol
f
MAX
T
A
=
–40°C
to +85°C
Min.
70
45
110
75
11.9
15.4
7.3
9.3
12.3
15.8
7.7
9.7
10
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
14.0
17.5
8.5
10.5
14.5
18.0
9.0
11.0
10
pF
pF
ns
ns
Parameter
Maximum Clock
Frequency
V
CC
(V)
3.3 ± 0.3
5.0 ± 0.5
Conditions
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
V
CC
=
Open
(3)
Min.
80
50
130
90
Typ.
125
75
170
115
6.7
9.2
4.6
6.1
7.6
10.1
4.8
6.3
4
25
Max.
Max.
Units
MHz
t
PLH
, t
PHL
Propagation Delay
Time (CK-Q, Q)
3.3 ± 0.3
5.0 ± 0.5
t
PLH
, t
PHL
Propagation Delay
Time (CLR, PR -Q, Q)
3.3 ± 0.3
5.0 ± 0.5
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
Note:
3. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I
CC
(opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 2 (per F/F).
AC Operating Requirements
T
A
=
25°C
Symbol
t
W
(L), t
W
(H)
t
W
(L)
t
S
t
H
t
REC
T
A
=
–40°C
to +85°C
Guaranteed
Minimum
Units
ns
ns
ns
ns
ns
Parameter
Minimum Pulse Width (CK)
Minimum Pulse Width (CLR, PR)
Minimum Setup Time
Minimum Hold Time
Minimum Recovery Time (CLR, PR)
V
CC
(V)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
(4)
Typ.
6.0
5.0
6.0
5.0
6.0
5.0
0.5
0.5
5.0
3.0
7.0
5.0
7.0
5.0
7.0
5.0
0.5
0.5
5.0
3.0
Note:
4. V
CC
is 3.3 ± 0.3V or 5.0 ± 0.5V
©1992 Fairchild Semiconductor Corporation
74VHC74 Rev. 1.3.0
www.fairchildsemi.com
5
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