74LCX06 — Low Voltage Hex Inverter/Buffer with Open Drain Outputs
January 2008
74LCX06
Low Voltage Hex Inverter/Buffer with Open
Drain Outputs
Features
■
5V tolerant inputs
■
2.3V–3.6V V
CC
specifications provided
■
3.7ns t
PD
max. (V
CC
=
3.3V), 10µA I
CC
max.
■
Power down high impedance inputs and outputs
■
±24mA output drive (V
CC
=
3.0V)
■
Implements p
roprietary
noise/EMI reduction circuitry
■
Latch-up performance exceeds 500mA
■
ESD performance:
General Description
The LCX06 contains six inverters/buffers. The inputs tol-
erate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
The outputs of the LCX06 are open drain and can be
connected to other open drain outputs to implement
active LOW wire AND or active HIGH wire OR functions.
The 74LCX06 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
– Human body model
>
2000V
– Machine model
>
200V
Ordering Information
Package
Order Number Number
74LCX06M
74LCX06SJ
74LCX06MTC
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
www.fairchildsemi.com
©1999 Fairchild Semiconductor Corporation
74LCX06 Rev. 1.8.0
74LCX06 — Low Voltage Hex Inverter/Buffer with Open Drain Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
I
IK
I
OK
Supply Voltage
DC Input Voltage
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to +7.0V
–50mA
–50mA
+50mA
+50mA
±100mA
±100mA
–65°C to +150°C
DC Output Voltage, Output in HIGH or LOW State
(1)
DC Input Diode Current, V
I
<
GND
DC Output Diode Current
V
O
<
GND
V
O
>
V
CC
I
O
I
CC
I
GND
T
STG
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
(2)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
Operating
Data Retention
V
I
V
O
I
OL
Input Voltage
Output Voltage
Output Current
V
CC
=
3.0V–3.6V
V
CC
=
2.7V–3.0V
V
CC
=
2.3V–2.7V
T
A
∆
t /
∆
V
Parameter
Min.
2.0
1.5
0
0
Max.
3.6
3.6
5.5
5.5
+24
+12
+8
Units
V
V
V
mA
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
°C
ns / V
Note:
2. Unused inputs must be held HIGH or LOW. They may not float.
©1999 Fairchild Semiconductor Corporation
74LCX06 Rev. 1.8.0
www.fairchildsemi.com
2
74LCX06 — Low Voltage Hex Inverter/Buffer with Open Drain Outputs
DC Electrical Characteristics
T
A
=
–40°C to +85°C
Symbol
V
IH
V
IL
V
OL
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
LOW Level Output Voltage
V
CC
(V)
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
2.7
3.0
Conditions
Min.
1.7
2.0
Max.
Units
V
0.7
0.8
I
OL
=
100µA
I
OL
=
8mA
I
OL
=
12mA
I
OL
=
16mA
I
OL
=
24mA
0
≤
V
I
≤
5.5V
V
I
or V
O
=
5.5V
V
I
=
V
CC
or GND
3.6V
≤
V
I
≤
5.5V
V
IH
=
V
CC
– 0.6V
V
O
=
5.5V
0.2
0.6
0.4
0.4
0.55
±5.0
10
10
±10
500
10
V
V
I
I
I
OFF
I
CC
∆
I
CC
I
OHZ
Input Leakage Current
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
Off State Current
2.3–3.6
0
2.3–3.6
2.3–3.6
2.0–3.6
µA
µA
µA
µA
µA
AC Electrical Characteristics
T
A
=
–40°C to +85°C, R
L
=
500
Ω
V
CC
=
3.3V ± 0.3V,
C
L
=
50pF
Symbol
t
PZL
, t
PLZ
V
CC
=
2.7V,
C
L
=
50pF
Min.
1.0
V
CC
=
2.5V ± 0.2V,
C
L
=
30pF
Min.
0.8
Parameter
Propagation Delay Time
Min.
0.8
Max.
3.7
Max.
4.1
Max.
3.5
Units
ns
Dynamic Switching Characteristics
T
A
=
25°C
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
V
CC
(V)
3.3
2.5
3.3
2.5
Conditions
C
L
=
50pF, V
IH
=
3.3V, V
IL
=
0V
C
L
=
30pF, V
IH
=
2.5V, V
IL
=
0V
C
L
=
50pF, V
IH
=
3.3V, V
IL
=
0V
C
L
=
30pF, V
IH
=
2.5V, V
IL
=
0V
Typical
0.9
0.7
–0.8
–0.6
Unit
V
V
Capacitance
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
Open, V
I
=
0V or V
CC
V
CC
=
3.3V, V
I
=
0V or V
CC
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10MHz
Typical
7
8
25
Units
pF
pF
pF
©1999 Fairchild Semiconductor Corporation
74LCX06 Rev. 1.8.0
www.fairchildsemi.com
3
74LCX06 — Low Voltage Hex Inverter/Buffer with Open Drain Outputs
AC Loading and Waveforms
(Generic for LCX Family)
Test
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
Open
6V at V
CC
=
3.3 ± 0.3V
V
CC
x 2 at V
CC
=
2.5 ± 0.2V
GND
Switch
Figure 1. AC Test Circuit (C
L
includes probe and jig capacitance)
3-STATE Output Low Enable and
Disable Times for Logic
V
CC
Symbol
V
mi
V
mo
V
x
V
y
t
rise
and t
fall
3.3V ± 0.3V
1.5V
1.5V
V
OL
+ 0.3V
V
OH
– 0.3V
2.7V
1.5V
1.5V
V
OL
+ 0.3V
V
OH
– 0.3V
2.5V ± 0.2V
V
CC
/ 2
V
CC
/ 2
V
OL
+ 0.15V
V
OH
– 0.15V
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t
r
= t
f
= 3ns)
©1999 Fairchild Semiconductor Corporation
74LCX06 Rev. 1.8.0
www.fairchildsemi.com
4
74LCX06 — Low Voltage Hex Inverter/Buffer with Open Drain Outputs
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
PIN ONE
INDICATOR
1
7
1.70
1.27
1.27
(0.33)
0.51
0.35
0.25
M
LAND PATTERN RECOMMENDATION
C B A
1.75 MAX
1.50
1.25
0.25
0.10
C
0.10 C
SEE DETAIL A
0.25
0.19
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1999 Fairchild Semiconductor Corporation
74LCX06 Rev. 1.8.0
www.fairchildsemi.com
5
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