74VHCT08A — Quad 2-Input AND Gate
February 2008
74VHCT08A
Quad 2-Input AND Gate
Features
■
High speed: t
PD
=
5.0ns (typ.) at T
A
=
25°C
■
High noise immunity: V
IH
=
2.0V, V
IL
=
0.8V
■
Power down protection is provided on all inputs and
General Description
The VHCT08A is an advanced high speed CMOS 2
Input AND Gate fabricated with silicon gate CMOS tech-
nology. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 4 stages including
buffer output, which provide high noise immunity and
stable output.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
CC
=
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
outputs
■
Low noise: V
OLP
=
0.8V (max.)
■
Low power dissipation: I
CC
=
2µA (max.) @ T
A
=
25°C
■
Pin and function compatible with 74HCT08
Ordering Information
Order Number
74VHCT08AM
74VHCT08ASJ
74VHCT08AMTC
74HCT08AN
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1997 Fairchild Semiconductor Corporation
74VHCT08A Rev. 1.3.0
www.fairchildsemi.com
74VHCT08A — Quad 2-Input AND Gate
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
Truth Table
A
L
L
H
H
B
L
H
L
H
O
L
L
L
H
©1997 Fairchild Semiconductor Corporation
74VHCT08A Rev. 1.3.0
www.fairchildsemi.com
2
74VHCT08A — Quad 2-Input AND Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
DC Input Voltage
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–0.5V to +7.0V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
DC Output Voltage
HIGH or LOW state, I
OUT
absolute maximum rating must be observed
V
CC
=
0V
Input Diode Current
Output Diode Current, V
OUT
<
GND, V
OUT
>
V
CC
(Outputs Active)
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
Supply Voltage
Input Voltage
Parameter
Rating
4.5V to 5.5V
0V to +5.5V
0V to V
CC
0V to +5.5V
–40°C to +85°C
0ns/V
∼
20ns/V
Output Voltage
HIGH or LOW state, I
OUT
absolute maximum rating must be observed
V
CC
=
0V
Operating Temperature
Input Rise and Fall Time, V
CC
=
5.0V ± 0.5V
T
OPR
t
r
, t
f
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1997 Fairchild Semiconductor Corporation
74VHCT08A Rev. 1.3.0
www.fairchildsemi.com
3
74VHCT08A — Quad 2-Input AND Gate
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
CC
I
CCT
I
OFF
T
A
=
–40°C
to +85°C
Min.
2.0
2.0
0.8
0.8
0.8
0.8
4.40
3.80
0.1
0.1
0.44
±1.0
20.0
1.50
5.0
µA
µA
mA
µA
V
V
V
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Maximum I
CC
/ Input
Output Leakage
Current (Power
Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
0–5.5
5.5
5.5
0.0
Conditions
Min.
2.0
2.0
Typ. Max.
Max. Units
V
V
IN
=
V
IH
I
OH
=
–50µA
or V
IL
I
OH
=
–8mA
V
IN
=
V
IH
I
OL
=
50µA
or V
IL
I
OL
=
8mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
IN
=
3.4V, Other
Inputs
=
V
CC
or GND
V
OUT
=
5.5V
4.40
3.94
4.50
0.0
0.36
±0.1
2.0
1.35
0.5
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(2)
V
OLV(2)
V
IHD(2)
V
ILD(2)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
Typ.
0.4
–0.4
Limits
0.8
–0.8
2.0
0.8
Units
V
V
V
V
Note:
2. Parameter guaranteed by design.
©1997 Fairchild Semiconductor Corporation
74VHCT08A Rev. 1.3.0
www.fairchildsemi.com
4
74VHCT08A — Quad 2-Input AND Gate
AC Electrical Characteristics
T
A
=
25°C
Symbol
t
PLH
, t
PHL
C
IN
C
PD
T
A
=
–40°C to
+85°C
Max
6.9
7.9
10
Parameter
Propagation Delay
Input Capacitance
Power Dissipation
Capacitance
V
CC
(V) Conditions
5.0 ± 0.5 C
L
=
15pF
C
L
=
50pF
V
CC
=
Open
(3)
Min
Typ
5.0
5.5
4
18
Min
1.0
1.0
Max
8.0
9.0
10
Units
ns
pF
pF
Note:
3. C
PD
is defined as the value of the internal equivalent capacitance, which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I
CC
(opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 4 (per gate)
©1997 Fairchild Semiconductor Corporation
74VHCT08A Rev. 1.3.0
www.fairchildsemi.com
5
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