NBXDBB018, NBXDBA018
3.3 V, 155.52 MHz /
311.04 MHz LVPECL Clock
Oscillator
The NBXDBB018 dual frequency crystal oscillator (XO) is
designed to meet today’s requirements for 3.3 V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable 155.52
MHz or 311.04 MHz, ultra low jitter and phase noise LVPECL
differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000. Frequency stability options available as
either 50 PPM NBXDBA018 (Industrial Temperature Range) or
20 PPM NBXDBB018 (Commercial Temperature Range).
Features
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6 PIN CLCC
LN SUFFIX
CASE 848AB
MARKING DIAGRAM
NBXDBA018
155.52/311.04
AAWLYYWWG
NBXDBB018
155.52/311.04
AAWLYYWWG
•
•
•
•
•
•
•
•
•
LVPECL Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise
−
0.4 ps (12 kHz
−
20 MHz)
Selectable Output Frequency
−
155.52 MHz (default) / 311.04 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range 3.3 V
±10%
Total Frequency Stability
−
±20
PPM or
±50
PPM
This is a Pb−Free Device
NBXDBA018
NBXDBB018
155.52/311.04
AA
WL
YY
WW
G
= NBXDBA018 (±50 PPM)
= NBXDBB018 (±20 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NBXDBB018LN1TAG
NBXDBA018LN1TAG
Package
CLCC−6
(Pb−Free)
CLCC−6
(Pb−Free)
CLCC−6
(Pb−Free)
CLCC−6
(Pb−Free)
Shipping
†
1000/
Tape & Reel
1000/
Tape & Reel
100/
Tape & Reel
100/
Tape & Reel
Applications
•
Networking
•
SONET
•
SDH
V
DD
6
CLK CLK
5 4
NBXDBB018LNHTAG
NBXDBA018LNHTAG
Crystal
PLL
Clock
Multiplier
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
3
GND
1
OE
2
FSEL
Figure 1. Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 3
1
Publication Order Number:
NBXDBB018/D
NBXDBB018, NBXDBA018
OE
FSEL
GND
1
2
3
6
5
4
V
DD
CLK
CLK
Figure 2. Pin Connections
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
Symbol
OE
I/O
LVTTL/LVCMOS
Control Input
LVTTL/LVCMOS
Control Input
Power Supply
Description
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁ ÁÁÁÁ
Á
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Á
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁ ÁÁÁÁ
Á
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁ ÁÁÁÁ
Á
Á Á
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Á
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
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Á Á Á Á Á ÁÁÁ ÁÁÁÁ
Á Á
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Á
Á Á
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Á
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁ ÁÁÁÁ
Á
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁ ÁÁÁÁ
Á Á Á Á Á ÁÁÁ ÁÁÁÁ
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁ ÁÁÁÁ
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Á
Á Á
FSEL
GND
CLK
CLK
V
DD
Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output
Frequency Select pin description Table 3.
Ground 0 V
LVPECL Output
LVPECL Output
Power Supply
Non−Inverted Clock Output. Typically loaded with 50
W
receiver termination resistor to
V
TT
= V
DD
−
2 V.
Inverted Clock Output. Typically loaded with 50
W
receiver termination resistor to
V
TT
= V
DD
−
2 V.
Positive power supply voltage. Voltage should not exceed 3.3 V
±10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Open
HIGH Level
LOW Level
Output Pins
Active
Active
High Z
Table 3. OUTPUT FREQUENCY SELECT
FSEL Pin
Open
(pin will float high)
HIGH Level
LOW Level
Output Frequency (MHz)
155.52
155.52
311.04
Table 4. ATTRIBUTES
Characteristic
Input Default State Resistor
ESD Protection
Human Body Model
Machine Model
Value
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
V
DD
I
out
T
A
T
stg
T
sol
Parameter
Positive Power Supply
LVPECL Output Current
Operating Temperature Range
Storage Temperature Range
Wave Solder
See Figure 6
Condition 1
GND = 0 V
Continuous
Surge
Condition 2
Rating
4.6
25
50
−40
to +85
−55
to +120
260
Units
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NBXDBB018, NBXDBA018
Table 6. DC CHARACTERISTICS
(V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 2)
Symbol
I
DD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
OUTPP
Characteristic
Power Supply Current (Note 2)
OE and FSEL Input HIGH Voltage
OE and FSEL Input LOW Voltage
Input HIGH Current
Input LOW Current
OE
FSEL
OE
FSEL
V
DD
= 3.3 V
Output LOW Voltage (Note 2)
V
DD
= 3.3 V
Output Voltage Amplitude (Note 2)
2000
GND
−
300
−100
−100
−100
−100
V
DD
−1195
2105
V
DD
−1945
1355
670
Conditions
Min.
Typ.
78
Max.
100
V
DD
800
+100
+100
+100
+100
V
DD
−945
2355
V
DD
−1600
1700
Units
mA
mV
mV
mA
mA
mV
mV
mV
Output HIGH Voltage (Note 2)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50
W
to V
DD
−
2.0 V.
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3
NBXDBB018, NBXDBA018
Table 7. AC CHARACTERISTICS
(V
DD
= 3.3 V
±
10%, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 3)
Symbol
f
CLKOUT
Characteristic
Output Clock Frequency
Conditions
FSEL = HIGH
FSEL = LOW
Df
Frequency Stability
−
NBXDBB018
−
NBXDBA018
Phase−Noise Performance
f
CLKout
= 155.52 MHz/311.04 MHz
(See Figures 3 and 4)
0°C to +70°C
−40°C
to +85°C
(Note 4)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
t
jit
(F)
t
jitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
Period, Peak−to−Peak
t
OE/OD
t
DUTY_CYCLE
t
R
t
F
t
start
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
Output Rise Time (20% and 80%)
Output Fall Time (80% and 20%)
Startup Time
Aging
1
st
Year
Every Year After 1
st
48
50
250
250
1
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10000 Cycles
10000 Cycles
−105/−102
−122/−115
−129/−122
−129/−122
−137/−131
−160/−156
0.4
2
13
1
9
0.9
8
30
4
20
200
52
400
400
5
3
1
Min.
Typ.
155.52
311.04
±20
±50
ppm
Max.
Units
MHz
F
NOISE
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
ps
ps
ps
ns
%
ps
ps
ms
ppm
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50
W
to V
DD
−
2.0 V.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
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4
NBXDBB018, NBXDBA018
Figure 3. Typical Phase Noise Plot at 155.52 MHz
Figure 4. Typical Phase Noise Plot at 311.04 MHz
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