NBVSPA013
2.5 V, 212.00 MHz LVDS
Voltage-Controlled Clock
Oscillator (VCXO)
PureEdget Product Series
The NBVSPA013 voltage−controlled crystal oscillator (VCXO) is
designed to meet today’s requirements for 2.5 V LVDS clock
generation applications. These devices use a high Q fundamental
mode crystal and Phase Locked Loop (PLL) multiplier to provide
212.00 MHz with a pullable range of
±100
ppm and a frequency
stability of
±50
ppm. The silicon−based PureEdget products design
provides users with exceptional frequency stability and reliability.
They produce an ultra low jitter and phase noise LVDS differential
output.
The NBVSPA013 is a member of ON Semiconductor’s PureEdge
clock family that provides accurate and precision clock generation
solutions.
Available in the industry standard 5.0 x 7.0 x 1.8 mm SMD (CLCC)
package on 16 mm tape and reel in quantities of 1,000 and 100.
Features
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MARKING DIAGRAMS
6 PIN CLCC
LN SUFFIX
CASE 848AB
A
WL
YY
WW
G
NBVSPA013
212.0000
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
LVDS Differential Output
Uses High Q Fundamental Mode Crystal
Ultra Low Jitter and Phase Noise
−
0.5 ps (12 kHz
−
20 MHz)
Pullable Range Minimum of
±100
ppm
Frequency Stability of
±50
ppm
Control Voltage with Positive Slope
Voltage Control Linearity of
±10%
Hermetically Sealed Ceramic SMD Packages of size 5.0 x 7.0 x
1.8 mm
•
Operating Range: 2.5 V
±5%
•
These Devices are Pb−Free and are RoHS Compliant
Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 6 of this data sheet.
•
Networking
•
Networking Base Stations
•
Broadcasting
©
Semiconductor Components Industries, LLC, 2012
April, 2012
−
Rev. 0
1
Publication Order Number:
NBVSPA013/D
NBVSPA013
V
DD
6
CLK CLK
5 4
Crystal
PLL
Clock
Multiplier
LVDS
1
V
C
2
OE
3
GND
Figure 1. Simplified Logic Diagram
V
C
OE
GND
1
2
3
6
5
4
V
DD
CLK
CLK
Figure 2. Pin Connections
(Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
Symbol
V
C
(Note 1)
OE
GND
CLK
CLK
V
DD
I/O
Analog Input
LVTTL/LVCMOS
Control Input
Power Supply
LVDS Output
LVDS Output
Power Supply
Description
Analog control voltage input pin that adjusts output oscillation frequency. f
0
=V
C
= 1.25 V
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
Ground at 0 V. Electrical and Case Ground.
Non−Inverted Clock Output. Typically loaded with 100
W
receiver termination resistor
across differential pair.
Inverted Clock Output. Typically loaded with 100
W
receiver termination resistor across
differential pair.
Positive Power Supply Voltage. Voltage should not exceed 2.5 V
±5%.
1. Control voltage has a positive slope with a typical linearity of
±10%;
V
C
= 1.25 V
±
1 V.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Open
HIGH Level
LOW Level
Output Pins
Active
Active
High Z
Table 3. ATTRIBUTES
Characteristic
Input Default State Resistor
ESD Protection
Human Body Model
Machine Model
Value
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
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2
NBVSPA013
Table 4. MAXIMUM RATINGS
Symbol
V
DD
V
IN
I
OSC
T
A
T
stg
T
sol
Parameter
Positive Power Supply
Control Input (V
C
and OE)
Output Short Circuit Current
CLK to CLK
CLK or CLK to GND
Operating Temperature Range
Storage Temperature Range
Wave Solder
See Figure 5
Continuous
Continuous
Condition 1
GND = 0 V
V
IN
≤
V
DD
+ 200 mV
V
IN
≥
GND
−
200 mV
12
24
−40
to +85
−55
to +120
260
Condition 2
Rating
4.6
Units
V
V
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. DC CHARACTERISTICS
(V
DD
= 2.5 V
±5%,
GND = 0 V, T
A
=
−40°C
to +85°C) (Note 2)
Symbol
I
DD
V
IH
V
IL
I
IH
I
IL
DV
OD
V
OS
DV
OS
V
OH
V
OL
V
OD
Characteristic
Power Supply Current
OE and FSEL Input HIGH Voltage
OE and FSEL Input LOW Voltage
Input HIGH Current
Input LOW Current
Change in Magnitude of V
OD
for
Complementary Output States
Offset Voltage
Change in Magnitude of V
OS
for
Complementary Output States
Output HIGH Voltage
Output LOW Voltage
Differential Output Voltage
900
250
(Note 3)
OE
OE
(Note 3)
2000
GND
−
300
−100
−100
0
1125
0
1
1425
1075
450
1
Conditions
Min.
Typ.
75
Max.
100
V
DD
800
+100
+100
25
1375
25
1600
Units
mA
mV
mV
mA
mA
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
3. Parameter guaranteed by design verification not tested in production.
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3
NBVSPA013
Table 6. AC CHARACTERISTICS
(V
DD
= 2.5
±5%,
GND = 0 V, T
A
=
−40°C
to +85°C) (Note 4)
Symbol
f
CLKOUT
Df
t
jit
(f)
t
jitter
Characteristic
Output Clock Frequency
Frequency Stability
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
Period, RMS
Period, Peak−to−Peak
t
OE/OD
F
P
V
C(bw)
t
DUTY_CYCLE
t
R
t
F
t
start
Output Enable/Disable Time
Crystal Pullability (Note 6)
Control Voltage Bandwidth
Output Clock Duty Cycle
(Measured at Cross Point)
Output Rise Time (20% and 80%)
Output Fall Time
(80% and 20%)
Start−up Time
Aging
1
st
Year
Every Year After 1
st
0 V
≤
V
C
≤
V
DD
−3
dB
±100
20
45
50
245
245
1
55
400
400
5
3
1
Conditions
NBVSPA013
(Note 5)
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
10,000 Cycles
10,000 Cycles
0.4
3
15
2
10
Min.
Typ.
212.00
±50
0.9
8
30
4
20
200
Max.
Unit
MHz
ppm
ps
ps
ps
ps
ps
ns
ppm
KHz
%
ps
ps
ms
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
6. Gain transfer is positive with a rate of 130 ppm/V.
Table 7. PHASE NOISE PERFORMANCE FOR NBVSPA013
Parameter
f
NOISE
Characteristic
Output Phase−Noise Performance
Condition
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
100 kHz of Carrier
1 MHz of Carrier
10 MHz of Carrier
212.00 MHZ
−82
−110
−122
−123
−132
−160
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
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4
NBVSPA013
Figure 3. Typical Phase Noise Plot at 212.00 MHz
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5
FPGA/CPLD
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