MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
8051 Embedded LCD Monitor Controller
with Flash OSD
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8051 core, 12MHz operating frequency with double CPU clock option, 3.3V power supply.
1024-byte RAM, 64K-byte program Flash-ROM.
Maximum 4 channels of 5V open-drain PWM DAC.
Maximum 32 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment.
Built-in low power reset circuit.
Compliant with VESA DDC2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
Maximum 4-channel 6-bit ADC.
Watchdog timer with programmable interval.
OSD controller features:
.
Full-screen display consists of 15 (rows) by 30 (columns) characters.
.
Programmable OSD menu positioning for display screen center.
.
512 Flash-ROM fonts, with 12x18 dot matrix, including 480 standard fonts and 32 multi-color fonts.
.
Character (per row) and window intensity control.
.
Character bordering, shadowing and blinking effect.
.
Character height control (18 to 71 lines), double height and/or width control.
.
4 programmable windows with multi-level operation and programmable shadowing width/height/color.
In System Programming function (ISP).
42-pin SDIP or 44-pin PLCC/QFP package.
GENERAL DESCRIPTIONS
The MTV230M micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA
DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal
OSD character Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P3.0-2
P3.4-5
P4.0-7
P5.0-7
RST
X1
X2
P0.0-7
P2.0-3
RD
WR
ALE
INT1
P0.0-7
P2.0-3
RD
WR
ALE
INT1
OSDHS
OSDVS
XIN
ROUT
GOUT
BOUT
FBKG
INT
HSYNC
VSYNC
HBLANK
VBLANK
ISCL
ISDA
HSCL
HSDA
XFR
OSD
CONTROL
8051
CORE
AD0-3
ADC
H/VSYNC
CONTROL
PWM DAC
DA0-3
DDC & IIC
INTERFACE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.0
-1-
2000/11/15
MYSON
TECHNOLOGY
PIN CONNECTION
OSDHS
OSDVS
P4.7/VBLANK
P4.6/HBLANK
X1
X2
P4.5
P4.4
P4.3
P4.2
P4.1/VSYNC
P4.0/HSYNC
P3.0/Rxd/HSCL
P3.1/Txd/HSDA
P3.2/INT0
7
8
9
10
11
12
13
14
15
16
17
MTV230M
(Rev 1.0)
MTV230M
44 Pin
PLCC
39
38
37
36
35
34
33
32
31
30
29
P1.3
P1.2
P1.1
P5.6/DA2
P5.5/DA1
P5.4/DA0
P5.3/AD3
P5.2/AD2
P5.1/AD1
P5.0/AD0
P1.7
P1.6
P1.5
P1.4
ROUT
XIN
OSDHS
OSDVS
P4.7/VBLANK
P4.6/HBLANK
X1
X2
P4.5
P4.4
P4.3
P4.2
P4.1/VSYNC
P4.0/HSYNC
P3.0/Rxd/HSCL
P3.1/Txd/HSDA
P3.2/INT0
VDD
RST
VSS
P3.4/T0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MTV230M
42 Pin
SDIP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GOUT
BOUT
FBKG
INT/P6.2
P5.7/DA3
P5.6/DA2
P5.5/DA1
P5.4/DA0
P5.1/AD1
P5.0/AD0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P6.1/ISDA
P6.0/ISCL
P3.5/T1
P5.7/DA3
INT/P6.2
FBKG
BOUT
GOUT
ROUT
XIN
40
41
42
43
44
1
2
3
4
5
6
28
27
26
25
24
23
22
21
20
19
18
P6.0/ISCL
P3.5/T1
P3.4/T0
VSS
RST
VDD
P1.0
P6.1/ISDA
Revision 1.0
-2-
2000/11/15
MYSON
TECHNOLOGY
PIN CONFIGURATION
MTV230M
(Rev 1.0)
A “CMOS pin” can be used as Input or Output mode. To use these pins as output mode, S/W needs to set
the corresponding output enable control bit “P
xx
oe” to 1. Otherwise, the “P
xx
oe” should clear to 0. In Output
mode, these pins can sink and drive at least 4mA current.
A “5V open drain pin” means it can sink at least 4mA current but no drive current to VDD. It can be used as
input or output function and needs an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output low level, and
drive at least 4mA current for 160nS when output transit from low to high, then keep drive 100uA to maintain
the pin at a high level. It can be used as input or output function. It needs an external pull up resistor when
driving heavy load device.
4mA
10uA
120uA
2 OSC
period
delay
4mA
Output
Data
Input
Data
8051 Standard Pin
Pin
No Current
Input
Data
4mA
Output
Data
Pin
5V Open Drain Pin
4mA
No Current
Output
Data
4mA
Pin
Input
Data
Pin
No Current
Input
Data
CMOS Pin (Output Mode)
P
xx
oe = 1
CMOS Pin (Input Mode)
P
xx
oe = 0
Revision 1.0
-3-
2000/11/15
MYSON
TECHNOLOGY
PIN DESCRIPTION
Name
RST
VDD
VSS
X2
X1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/Rxd/HSCL
P3.1/Txd/HSDA
P3.2/INT0
P3.4/T0
P3.5/T1
P4.7/VBLANK
P4.6/HBLANK
P4.5/HCLAMP
P4.4
P4.3
P4.2
P4.1/VSYNC
P4.0/HSYNC
P5.7/DA3
P5.6/DA2
P5.5/DA1
P5.4/DA0
P5.3/AD3
P5.2/AD2
P5.1/AD1
P5.0/AD0
P6.0/ISCL
P6.1/ISDA
INT/P6.2
FBKG
BOUT
GOUT
ROUT
XIN
OSDHS
OSDVS
Type
I
-
-
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
#44/42
MTV230M
(Rev 1.0)
Description
Active high reset
Positive Power Supply
Ground
Oscillator output
Oscillator input
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O / Rxd / Slave IIC clock (5V open drain)
General purpose I/O / Txd / Slave IIC data (5V open drain)
General purpose I/O / INT0 (8051 standard)
General purpose I/O / T0 (8051 standard)
General purpose I/O / T1 (8051 standard)
General purpose I/O / Vertical blank output (CMOS)
General purpose I/O / Horizontal blank output (CMOS)
General purpose I/O / Hclamp output (CMOS)
General purpose I/O (CMOS)
General purpose I/O (CMOS)
General purpose I/O (CMOS)
General purpose I/O / Vsync input (5V open drain)
General purpose I/O / Hsync or Xsync input (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose output / Master IIC clock (5V open drain)
General purpose output / Master IIC data (5V open drain)
OSD intensity output / General purpose output (CMOS)
OSD fast blanking output (CMOS)
OSD blue color video signal output (CMOS)
OSD green color video signal output (CMOS)
OSD red color video signal output (CMOS)
OSD pixel clock input (CMOS)
OSD vertical SYNC input (CMOS)
OSD horizontal SYNC input (CMOS)
19
18
20
8
7
25
26
27
28
29
30
31
32
15
16
17
21
22
5
6
9
10
11
12
13
14
40/38
39/37
38/36
37/35
36/-
35/-
34
33
23
24
41/39
42/40
43/41
44/42
1
2
3
4
Revision 1.0
-4-
2000/11/15
MYSON
TECHNOLOGY
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV230M
(Rev 1.0)
The CPU core of MTV230M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and serial interface. The CPU core
fetches its program code from the 64K bytes Flash in MTV230M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz X’
tal
is applied on MTV230M, but the peripherals (IIC, DDC, H/V processor ) still run at the original frequency.
Note: All registers listed in this document reside in 8051’ external RAM area (XFR). For internal RAM
s
memory map, please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV230M, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for OSD control or other special function. Program can use "MOVX" instruction to access these
registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 768 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - AFFh. Program can
use "MOVX" instruction to access the AUXRAM.
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
SFR
Accessible by
direct addressing
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
80h
7Fh
Internal RAM
Accessible by
direct and indirect
addressing
F00h
AFFh
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
00h
800h
Revision 1.0
-5-
2000/11/15
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
