MYSON
TECHNOLOGY
MTV212M64
(Rev. 1.2)
8051 Embedded Monitor Controller
MTP Type
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8051 core, 12MHz operating frequency.
1024-byte RAM, 64K-byte program Flash-ROM.
•
Maximum 14 channels of 9V open-drain PWM DAC.
Maximum 32 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment
and programmable clamp pulse output.
Built-in self-test pattern generator with three free-running timings.
Built-in low power reset circuit.
Compliant with VESA DDC1/2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
4-channel 6-bit ADC.
Watchdog timer with programmable interval.
Compliant with Low Speed USB Spec.1.1 including 2 Endpoints: one is Control endpoint (8-byte IN & 8-
byte OUT FIFOs), the other one is Interrupt endpoint (8-byte IN FIFO).
Built-in 3.3V regulator for USB Interface.
40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212M micro-controller is an 8051 CPU core embedded device specially tailored to Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC processor, 14 built-in PWM DACs,
VESA DDC interface, 4-channel A/D converter, Low Speed USB Interface and a 64K-byte internal program
Flash-ROM.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.2
-1-
2000/07/04
MYSON
TECHNOLOGY
DEVICE SUMMARY
MTV212M64
(Rev. 1.2)
The MTV212M is the MTP (Multi-Time Programming) type device for all of MTV212A mask ROM derivatives,
the memory size and package differences please see the table below:
Part Number
MTV212A16
MTV212A24
MTV212A32
MTV212A32U
MTV212A48U
MTV212A64U
USB
No
No
No
Yes
Yes
Yes
ROM
16K
24K
32K
32K
48K
64K
RAM
256
512
512
768
768
1024
Package
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
The use of Auxiliary RAM (AUXRAM) is limited for targeted mask ROM, the allowable XBANK (35h) bank
selection is defined as the table below:
Part Number
MTV212A16
MTV212A24
MTV212A32
MTV212A32U
RAM
256
512
512
768
Xbnk2
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Xbnk1
-
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Xbnk0
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MTV212A48U
768
MTV212A64U
1024
Remark:
The major pin connection differences between USB (MTV212M64U) and non-USB (MTV212M64) types are
pin# 4, #5 and #6 for SDIP42 and PLCC44. The pin name of USB device is V33CAP(#4), VM(#5) and
VP(#6), while NC (No Connection) for non-USB device.
Revision 1.2
-2-
2000/07/04
MYSON
TECHNOLOGY
PIN CONNECTION
MTV212M64
(Rev. 1.2)
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MTV212M
40 Pin
PDIP #1
Non-USB
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.7/DA13
P2.6/DA12
P2.5/DA11
P2.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP
DM
DP
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MTV212M
40 Pin
PDIP #2
USB
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
P1.6
P1.5
P1.4
DA0/P5.0
V33CAP/NC
DM/NC
DP/NC
DA2/P5.2
DA1/P5.1
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC
DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP/NC
DM/NC
DP/NC
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MTV212M
42 Pin
SDIP
USB
or
Non-USB
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.6/DA12
P2.5/DA11
P2.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
P1.6
P1.5
40
41
42
43
44
1
2
3
4
5
6
RST
VDD
P2.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
7
8
9
10
11
12
13
14
15
16
17
MTV212M
44 Pin
PLCC
USB
or
Non-USB
28
27
26
25
24
23
22
21
20
19
18
P1.5
P1.4
P1.3
P1.2
P3.2/INT0
P1.1
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
P1.6
39
38
37
36
35
34
33
32
31
30
29
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.7/DA13
P2.6/DA12
P2.5/DA11
P2.4/DA10
HSCL/P3.0/Rxd
Revision 1.2
-3-
2000/07/04
MYSON
TECHNOLOGY
PIN DESCRIPTION
Name
DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP/NC
DM/NC
DP/NC
RST
VDD
P2.3/AD3
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd
HSCL/P3.0/Rxd
P2.4/DA10
P2.5/DA11
P2.6/DA12
P2.7/DA13
DA6/P5.6
DA7/HCLAMP
VBLANK/P4.0
HBLANK/P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC
Type
I/O
I/O
I/O
I/O
I/O
I/O
I
-
I/O
-
O
I
I/O
I/O
O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I/O
O
O
I
I
40
1
2
3
-
-
-
4
5
-
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin#
40 42
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
-
-
9
9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
-
30
-
31
-
-
30 32
31 33
32 34
33 35
34 36
35 37
36 38
37 39
38 40
39 41
40 42
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
MTV212M64
(Rev. 1.2)
Description
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / General purpose I/O (open drain).
3.3V Regulator Capacitor connection or NC.
USB DM or NC.
USB DP or NC.
Active high reset.
Positive Power Supply.
General purpose I/O / ADC Input.
Ground.
Oscillator output.
Oscillator input.
Master IIC data / General purpose I/O / T0.
Master IIC clock / General purpose I/O / T1.
Self-test video output / General purpose Output.
General purpose I/O / ADC Input.
General purpose I/O.
General purpose I/O.
General purpose Input / INT0.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O.
General purpose I/O / ADC Input.
General purpose I/O / ADC Input.
Slave IIC data / General purpose I/O / Txd.
Slave IIC clock / General purpose I/O / Rxd.
General purpose I/O / PWM DAC output (open drain).
General purpose I/O / PWM DAC output (open drain).
General purpose I/O / PWM DAC output (open drain).
General purpose I/O / PWM DAC output (open drain).
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / Hsync clamp pulse output (open drain).
Vertical blank / General purpose Output.
Horizontal blank / General purpose Output.
PWM DAC output / Vsync half freq. output (open drain).
PWM DAC output / Hsync half freq. output (open drain).
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / General purpose I/O (open drain).
Horizontal SYNC or Composite SYNC Input.
Vertical SYNC input.
Revision 1.2
-4-
2000/07/04
MYSON
TECHNOLOGY
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV212M64
(Rev. 1.2)
MTV212M includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within the
MTV212M.
1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.
1.3 INT1 input pin is not provided, it is connected to special interrupt sources.
1.4 Port2 are shared with special function pins.
In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV212M, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 768 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
divided into six banks, selected by XBANK register. Program can initialize Ri value and use "MOVX"
instruction to access the AUXRAM.
FFh
Internal RAM
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
SFR
Accessible by
direct addressing
80h
7Fh
Internal RAM
Accessible by
direct and indirect
addressing
00h
Revision 1.2
-5-
2000/07/04
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