MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
8051 Embedded CRT Monitor Controller
MASK Version
FEATURES
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8051 core.
384-bytes internal RAM.
16K-bytes program Mask ROM.
14-channels 10V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
28 bi-direction I/O pin,12 dedicated pin,12 shared with DAC,4 shared with DDC/IIC interface.
5-output pin shared with H/V sync output and self test output pins.
SYNC processor for composite separation, polarity and frequency check, and polarity adjustment.
Built-in monitor self-test pattern generator.
Built-in low power reset circuit.
One slave mode IIC interface and one master mode IIC interface.
IIC interface for DDC1/DDC2B and EEPROM; only one EEPROM needed to store DDC1/DDC2B and
display mode information.
Dual 4-bit ADC or 4 channel 6-bit ADC.
Watchdog timer with programmable interval.
40-pin PDIP and 44-pin PLCC package.
GENERAL DESCRIPTION
The MTV112A micro-controller is an 8051 CPU core embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 384-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface,
24Cxx series EEPROM interface, A/D converter and a 16K-bytes internal program Mask ROM.
BLOCK DIAGRAM
STOUT
P1.0-7
X1
P0.0-7
RD
WR
P0.0-7
RD
WR
XFR
HSYNC
H / VSYNC
CONTROL
VSYNC
HBLANK
VBLANK
X2
8051
CORE
INT
1
RST
WATCH-DOG
TIMER
RST
P2.0-3
P3.0-P3.2
14 CHANNEL
PWM DAC
DA0-9
DA10-13
P3.4 P2.4-7
ADC
AD0
AD1
HSCL
HSDA
DDC 1/2 B & FIFO
INTERFACE
ISCL
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV112A Revision 1.9 05/18/2001
1/20
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
P1.0
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
P1.5/AD3
P1.6/AD0
P1.7/AD1
RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
ISCL/P3.4/T0
VSYNC
HBLANK/P4.1
VBLANK/P4.0
X2
X1
VSS
VDD
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/P5.7
P1.0
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
P1.5/AD3
P1.6/AD0
P1.7/AD1
RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
ISCL/P3.4/T0
VSYNC
HCLAMP/P4.4
HBLANK/P4.1
VBLANK/P4.0
X2
X1
VSS
MTV112A
(Rev 1.9)
VDD
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/P5.7
DA8
MTV112A
DA8
DA9
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
P2.2
P2.1
P2.0/INT0
MTV112A
DA9
HALFH/P4.3
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
DA13/P2.4
P2.3
P2.2
P2.1
P2.0/INT0
P1.3/HCLAMP
P1.2/HALFH
P1.1/HALFV
P1.4/AD2
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
41
VDD
P1.0
6
5
4
3
2
1
44
43
42
NC
P1.5/AD3
P1.6/AD0
P1.7/AD1
RESET
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
ISCL/P3.4/T0
VSYNC
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
40
NC
39
38
37
36
35
DA4/P5.4
DA5/P5.5
DA6/P5.6
DA7/P5.7
DA8
DA9
STOUT/P4.2
DA10/P2.7
DA11/P2.6
DA12/P2.5
NC
MTV112A
34
33
32
31
30
29
X2
X1
P2.1
P2.2
P2.3
VBLANK/P4.0
HBLANK/P4.1
DA13/P2.4
VSS
P2.0/INT0
NC
MTV112A Revision 1.9 05/18/2001
2/20
MYSON
TECHNOLOGY
2.0 PIN DESCRIPTIONS
Name
P1.0
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
P1.5/AD3
P1.6/AD0
P1.7/AD1
RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
ISCL/P3.4/T0
VSYNC
HCLAMP/P4.4
HBLANK/P4.1
VBLANK/P4.0
X2
X1
VSS
P2.0/INT0
P2.1
P2.2
P2.3
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7
STOUT/P4.2
HALFH/P4.3
DA9
DA8
DA7/P5.7
DA6/P5.6
DA5/P5.5
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
VDD
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
O
O
O
O
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
-
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
-
30
31
32
33
34
35
36
37
38
39
40
Pin#
42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
-
19
20
21
22
23
24
25
26
27
28
30
31
32
33
-
34
35
36
37
38
39
41
42
43
44
1
Description
MTV112A
(Rev 1.9)
General purpose I/O
General purpose I/O / Vsync half frequency output.
General purpose I/O / Hsync half frequency output.
General purpose I/O / Hsync clamp pulse output.
General purpose I/O / ADC input.
General purpose I/O / ADC input.
General purpose I/O / ADC input
General purpose I/O / ADC input
Active high reset
IIC clock / General purpose I/O / Rxd
IIC data / General purpose I/O / Txd
IIC data / General purpose I/O / INT0
Horizontal SYNC or Composite SYNC
IIC clock / General purpose I/O / T0
Vertical SYNC
Hsync clamp pulse output / General purpose output
Horizontal blank / General purpose output
Vertical blank / General purpose output
Oscillator output
Oscillator input
Ground
General purpose I/O / INT0
General purpose I/O
General purpose I/O
General purpose I/O
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
Self-test video output / General purpose output
Hsync half frequency output / General purpose output
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
Positive power supply
MTV112A Revision 1.9 05/18/2001
3/20
MYSON
TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTION
1. 8051 CPU Core
MTV112A
(Rev 1.9)
MTV112A includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV112A.
1.2 Port 0, port 3.3, and ports 3.5 ~ 3.7 are not general-purpose I/O ports. They are dedicated to monitor
control or DAC pins.
1.3 INT1 and T1 input pins are not provided.
1.4 Ports 2.4 ~ 2.7 are shared with DAC pins; ports 3.0 ~ 3.2, and port3.4 are shared with monitor control
pins.
In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.
The Txd/Rxd (P3.0/P3.1) pins are shared with DDC interface. INT0/T0 pins are shared with IIC interface. An
extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature maintains an external
interrupt source when IIC interface is enabled.
Note: All registers listed in this document reside in the external RAM area (XFR). For the internal
RAM memory map please refer to the 8051 spec.
addr
PADMOD
30h (w)
PADMOD
31h (w)
PADMOD
37h (w)
Reg name
bit7
SINT0
P57E
-
bit6
IICF
P56E
-
bit5
DDCE
P55E
-
bit4
IICE
P54E
-
bit3
DA13E
P53E
-
bit2
DA12E
P52E
-
bit1
DA11E
P51E
-
bit0
DA10E
P50E
MORE
SINT0 = 1
=0
IICF
=1
=0
DDCE = 1
=0
IICE
=1
=0
DA13E = 1
=0
DA12E = 1
=0
DA11E = 1
=0
DA10E = 1
=0
P57E = 1
=0
P56E = 1
=0
P55E = 1
=0
P54E = 1
=0
P53E = 1
=0
P52E = 1
=0
→
INT0 source is pin #21.
→
INT0 source is pin #12.
→
Selects 400kHz master IIC speed.
→
Selects 100kHz master IIC speed.
→
Pin #10 is HSCL; pin #11 is HSDA.
→
Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.
→
Pin #12 is ISDA; pin #14 is ISCL.
→
Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.
→
Pin #25 is DA13.
→
Pin #25 is P2.4.
→
Pin #26 is DA12.
→
Pin #26 is P2.5.
→
Pin #27 is DA11.
→
Pin #27 is P2.6.
→
Pin #28 is DA10.
→
Pin #28 is P2.7.
→
Pin #32 is P5.7.
→
Pin #32 is DA7.
→
Pin #33 is P5.6.
→
Pin #33 is DA6.
→
Pin #34 is P5.5.
→
Pin #34 is DA5.
→
Pin #35 is P5.4.
→
Pin #35 is DA4.
→
Pin #36 is P5.3.
→
Pin #36 is DA3.
→
Pin #37 is P5.2.
→
Pin #37 is DA2.
MTV112A Revision 1.9 05/18/2001
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MYSON
TECHNOLOGY
=1
=0
P50E = 1
=0
MORE = 1
P51E
MTV112A
(Rev 1.9)
→
Pin #38 is P5.1.
→
Pin #38 is DA1.
→
Pin #39 is P5.0.
→
Pin #39 is DA0.
→
Bits P57E,P56E,P55E,P54E,P53E,P52E,P51E,P50E,DACK,EHALFV,
EHALFH,ENCLP,ADCMOD can be programmed,and master IIC speed is
controlled by (MCLK1,MCLK0) bits.
=0
→
above bits internal keep “0” by MTV112A, and master IIC speed is controlled by
IICF bit.
* SINT0 should be 0 in this case.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
SFR is a group of registers that is the same as standard 8051.
2.2 Internal RAM
There is a 384 bytes RAM in MTV112A. The first portion of the RAM area contains 256 bytes, accessible by
setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.
2.3 External Special Function Registers (XFR)
XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for
monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access
these registers.
FFH
80H
7FH
Accessible by indirect
addressing only.
The value of PSW.1 =
both 0 and 1.
(Using MOV A, @Ri
instruction)
Accessible by direct
and indirect
addressing.
PSW.1=0
SFR
Accessible by direct
addressing.
FFH
XFR
Accessible by indirect
external RAM
addressing.
(Using MOVX A, @Ri
Instruction.)
Accessible by direct
and indirect
addressing.
PSW.1 =1
00H
00H
3. PWM DAC
Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM clk
is X’ or 2 * X’ selected by DACK. And the frequency of these DAC outputs is (PWM clk frequency)/253
tal
tal,
or (PWM clk frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register
generates stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's
content is FFH. Writing 00H to the DAC register generates stable low output.
reg name
DA0
DA1
DA2
DA3
addr
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
bit7
DA0b7
DA1b7
DA2b7
DA3b7
bit6
DA0b6
DA1b6
DA2b6
DA3b6
bit5
DA0b5
DA1b5
DA2b5
DA3b5
bit4
DA0b4
DA1b4
DA2b4
DA3b4
5/20
bit3
DA0b3
DA1b3
DA2b3
DA3b3
bit2
DA0b2
DA1b2
DA2b2
DA3b2
bit1
DA0b1
DA1b1
DA2b1
DA3b1
bit0
DA0b0
DA1b0
DA2b0
DA3b0
MTV112A Revision 1.9 05/18/2001
嵌入式系统
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