SN54/74LS181
4-BIT ARITHMETIC
LOGIC UNIT
The SN54 / 74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic, operations on two variables and a variety of
arithmetic operations.
•
Provides 16 Arithmetic Operations Add, Subtract, Compare, Double,
Plus Twelve Other Arithmetic Operations
•
Provides all 16 Logic Operations of Two Variables Exclusive — OR,
Compare, AND, NAND, OR, NOR, Plus Ten other Logic Operations
•
Full Lookahead for High Speed Arithmetic Operation on Long Words
•
Input Clamp Diodes
4-BIT ARITHMETIC
LOGIC UNIT
LOW POWER SCHOTTKY
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC A1
24 23
B1
22
A2
21
B2
20
A3
19
B3
18
G Cn+4
17 16
P
15
A=B
14
F3
13
24
1
J SUFFIX
CERAMIC
CASE 623-05
N SUFFIX
PLASTIC
CASE 649-03
24
1
1
B0
2
A0
3
S3
4
S2
5
S1
6
S0
7
Cn
8
M
9
F0
10
F1
11 12
F2 GND
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
Ceramic
Plastic
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
LOGIC SYMBOL
PIN NAMES
LOADING
(Note a)
HIGH
A0 – A3, B0 – B3
S0 – S3
M
Cn
F0 – F3
A=B
G
P
Cn+4
Operand (Active LOW) Inputs
1.5 U.L.
Function — Select Inputs
2.0 U.L.
Mode Control Input
0.5 U.L.
Carry Input
2.5 U.L.
Function (Active LOW) Outputs
10 U.L.
Comparator Output
Open Collector
Carry Generator (Active LOW)
10 U.L.
Output
Carry Propagate (Active LOW)
10 U.L.
Output
Carry Output
10 U.L.
LOW
0.75 U.L.
1.0 U.L.
0.25 U.L.
1.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
10 U.L.
5 U.L.
5 (2.5) U.L.
7
8
6
5
4
3
Cn
M
2 1 23 22 21 20 19 18
A0 B0 A1 B1 A2 B2 A3 B3
Cn+4
A=B
G
P
F1
10
F2
11
F3
13
16
14
17
15
S0
S1
S2
S3 F
0
9
VCC = PIN 24
GND = PIN 12
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
FAST AND LS TTL DATA
5-332
SN54/74LS181
LOGIC DIAGRAM
7
8
2
1
23
22
21
20
19
18
Cn M
A0
B0
A1
B1 A2
B2 A3
B3
S0
S1
5
S2
6
4
S3
3
VCC = PIN 24
GND = PIN 12
= PIN NUMBERS
9
F0
10
F1
A=B
14
11
F2
13
F3
P
15
16
Cn+4
G
17
FUNCTIONAL DESCRIPTION
The SN54 / 74LS181 is a 4-bit high speed parallel Arithmetic
Logic Unit (ALU). Controlled by the four Function Select Inputs
(S0 . . . S3) and the Mode Control Input (M), it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands. The
Function Table lists these operations.
When the Mode Control Input (M) is HIGH, all internal
carries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control Input is
LOW, the carries are enabled and the device performs
arithmetic operations on the two 4-bit words. The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn+4 output, or
for carry lookahead between packages using the signals P
(Carry Propagate) and G (Carry Generate), P and G are not
affected by carry in. When speed requirements are not
stringent, the LS181 can be used in a simple ripple carry mode
by connecting the Carry Output (Cn+4) signal to the Carry Input
(Cn) of the next unit. For high speed operation the LS181 is
used in conjunction with the 9342 or 93S42 carry lookahead
circuit. One carry lookahead package is required for each
group of the four LS181 devices. Carry lookahead can be
provided at various levels and offers high speed capability
over extremely long word lengths.
The A = B output from the LS181 goes HIGH when all four F
outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A = B output is open collector and can be
wired-AND with other A = B outputs to give a comparison for
more then four bits. The A = B signal can also be used with the
Cn+4 signal to indicate A>B and A<B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one to
each operation. Thus, select code LHHL generates A minus B
minus 1 (2s complement notation) without a carry in and
generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition
(1s complement), a carry out means borrow; thus a carry is
generated when there is no underflow and no carry is
generated when there is underflow.
As indicated, the LS181 can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the operands
labeled inside the logic symbol.
FAST AND LS TTL DATA
5-333
SN54/74LS181
FUNCTION TABLE
MODE SELECT
INPUTS
S3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
S2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
ACTIVE LOW INPUTS
& OUTPUTS
LOGIC
(M = H)
ARITHMETIC**
(M = L) (Cn = L)
ACTIVE HIGH INPUTS
& OUTPUTS
LOGIC
(M = H)
ARITHMETIC**
(M = L) (Cn = H)
A
A minus 1
AB
AB minus 1
A+B
AB minus 1
Logical 1 minus 1
A+B
A plus (A + B)
B
AB plus (A + B)
A
⊕
B
A minus B minus 1
A+B
A+B
AB
A plus (A + B)
A
⊕
B
A plus B
B
AB plus (A + B)
A+B
A+B
Logical 0 A plus A*
AB
AB plus A
AB
AB plus A
A
A
A
A
A+B
A+B
AB
A+B
Logical 0 minus 1
AB
A plus AB
B
(A + B) plus AB
A
⊕
B
A minus B minus 1
AB
AB minus 1
A+B
A plus AB
A
⊕
B
A plus B
B
(A + B) plus AB
AB
AB minus 1
Logical 1 A plus A*
A+B
(A + B) plus A
A+B
(A + B) Plus A
A
A minus 1
L = LOW Voltage Level
H = HIGH Voltage Level
**Each
bit is shifted to the next more significant position
**Arithmetic operations expressed in 2s complement notation
LOGIC SYMBOLS
ACTIVE LOW OPERANDS
2 1 23 22 21 20 19 18
A0 B0 A1 B1 A2 B2 A3 B3
Cn+4
A=B
LS181
G
4 BIT ARITHMETIC
LOGIC UNIT
P
F1
10
F2
11
F3
13
ACTIVE HIGH OPERANDS
2 1 23 22 21 20 19 18
A0 B0 A1 B1 A2 B2 A3 B3
Cn+4
A=B
LS181
G
4 BIT ARITHMETIC
LOGIC UNIT
P
F1
10
F2
11
F3
13
7
8
6
5
4
3
Cn
M
16
14
17
15
7
8
6
5
4
3
Cn
M
16
14
17
15
S0
S1
S2
S3 F
0
9
S0
S1
S2
S3 F
0
9
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
VOH
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Output Voltage — High (A = B only)
Parameter
54
74
54
74
54, 74
54
74
54, 74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
5.5
Unit
V
°C
mA
mA
V
FAST AND LS TTL DATA
5-334
SN54/74LS181
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
Output LOW Voltage
Except G and P
VOL
Output G
Output P
IOH
Output HIGH Current
Input HIGH Current
Mode Input
Any A or B Input
Any S Input
Cn Input
Mode Input
Any A or B Input
Any S Input
Cn Input
Input LOW Current
Mode Input
Any A or B Input
Any S Input
Cn Input
Short Circuit Current (Note 2)
Power Supply Current
See Note 1A
ICC
See Note 1B
74
Note 1.
With outputs open, ICC is measured for the following conditions:
A. S0 through S3, M, and A inputs are at 4.5 V, all other inputs are grounded.
B. S0 through S3 and M are at 4.5 V, all other inputs are grounded.
Note 2: Not more than one output should be shorted at a time, nor for more than 1 second.
Min
2.0
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
IOL = 16 mA
IOL = 8.0 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
0.7
V
0.8
– 0.65
2.5
2.7
3.5
3.5
0.25
0.35
0.4
0.5
0.7
0.6
0.5
100
– 1.5
V
V
V
V
V
V
V
µA
54, 74
74
54, 74
54
74
54, 74
IIH
20
60
80
100
0.1
0.3
0.4
0.5
– 0.4
– 1.2
– 1.6
– 2.0
– 20
54
74
54
– 100
32
34
µA
VCC = MAX, VIN = 2.7 V
mA
VCC = MAX, VIN = 7.0 V
IIL
mA
VCC = MAX, VIN = 0.4 V
IOS
mA
VCC = MAX
mA
35
37
VCC = MAX
FAST AND LS TTL DATA
5-335
SN54/74LS181
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V, Pin 12 = GND, CL = 15 pF)
Limits
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Propagation Delay,
(Cn to Cn+4)
(Cn to F Outputs)
(A or B Inputs to G Output)
(A or B Inputs to G Output)
(A or B Inputs to P Output)
(A or B Inputs to P Output)
(AX or BX Inputs to FX Output)
(AX or BX Inputs to FX Output)
(AX or BX Inputs to FXH Outputs)
(AX or BX Inputs to FXH Outputs)
(A or B Inputs to F Outputs)
(A or B Inputs to Cn+4 Output)
(A or B Inputs to Cn+4 Output)
22
26
25
25
27
27
33
41
Min
Typ
18
13
17
13
19
15
21
21
20
20
20
22
21
13
21
21
Max
27
20
26
20
29
23
32
32
30
30
30
33
32
20
32
32
38
26
38
38
33
38
38
38
41
41
50
62
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
M = 0 V, (Sum or Diff Mode)
See Fig. 4 and Tables I and II
M = 0 V, (Sum Mode)
See Fig. 4 and Table I
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II
M = 4.5 V (Logic Mode)
See Fig. 4 and Table III
M = 0 V, S0 = S3 = 4.5 V, S1 = S2 = 0 V
(Sum Mode) See Fig. 6 and Table I
M = 0 V, S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode)
M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
RL = 2.0 kΩ
(Diff Mode) See Fig. 5 and Table II
(A or B Inputs to A = B Output)
ns
AC WAVEFORMS
INPUT
1.3 V
t
PLH
1.3 V
1.3 V
t
PHL
1.3 V
OUTPUT
Figure 4
A INPUT
1.3 V
1.3 V
INPUT
B INPUT
1.3 V
t
PLH
OUTPUT
1.3 V
1.3 V
t
PHL
1.3 V
t
PLH
OUTPUT
1.3 V
1.3 V
t
PHL
1.3 V
1.3 V
Figure 5
Figure 6
FAST AND LS TTL DATA
5-336
FPGA/CPLD
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