SN54/74LS85
4-BIT MAGNITUDE
COMPARATOR
The SN54/ 74LS85 is a 4-Bit Magnitude Camparator which compares two
4-bit words (A, B), each word having four Parallel Inputs (A0 – A3, B0 – B3); A3,
B3 being the most significant inputs. Operation is not restricted to binary
codes, the device will work with any monotonic code. Three Outputs are
provided: “A greater than B” (OA > B), “A less than B” (OA < B), “A equal to B”
(OA = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow cascading without
external gates. For proper compare operation, the Expander Inputs to the
least significant position must be connected as follows: IA < B= IA > B = L, IA = B
= H. For serial (ripple) expansion, the OA > B, OA < B and OA = B Outputs are
connected respectively to the IA > B, IA < B, and IA = B Inputs of the next most
significant comparator, as shown in Figure 1. Refer to Applications section of
data sheet for high speed method of comparing large words.
The Truth Table on the following page describes the operation of the
SN54 / 74LS85 under all possible logic conditions. The upper 11 lines describe
the normal operation under all conditions that will occur in a single device or
in a series expansion scheme. The lower five lines describe the operation
under abnormal conditions on the cascading inputs. These conditions occur
when the parallel expansion technique is used.
4-BIT MAGNITUDE
COMPARATOR
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
•
Easily Expandable
•
Binary or BCD Comparison
•
OA > B, OA < B, and OA = B Outputs Available
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
A3
15
B2
14
A2
13
A1
12
B1
11
A0
10
B0
9
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
NOTE:
The Flatpak version has the
same pinouts (Connection
Diagram) as the Dual In-Line
Package.
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
1
B3
2
3
4
5
6
7
8
IA<B IA=B
IA>B OA>B OA=B OA<B GND
LOGIC SYMBOL
PIN NAMES
LOADING
(Note a)
HIGH
A0 – A3, B0 – B3
IA = B
IA < B, IA > B
OA > B
OA < B
OA = B
Parallel Inputs
A = B Expander Inputs
A < B, A > B, Expander Inputs
A Greater Than B Output (Note b)
B Greater Than A Output (Note b)
A Equal to B Output (Note b)
1.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
LOW
0.75 U.L.
0.75 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
4
2
3
10 12 13 15 9 11 14 1
A0 A1 A2 A3 B0 B1 B2 B3
OA>B
IA>B
OA<B
IA<B
OA=B
IA=B
VCC = PIN 16
GND = PIN 8
5
7
6
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
FAST AND LS TTL DATA
5-84
SN54/74LS85
A n3
A n2
A n1
B n3
B n2
B n1
An
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3
OA > B
IA > B
IA < B
SN54/74LS85
OA < B
IA = B
OA = B
Bn
L
L
H
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
IA < B
SN54/74LS85
OA < B
OA = B
IA = B
A>B
A<B
A=B
L = LOW LEVEL
H = HIGH LEVEL
Figure 1. Comparing Two n-Bit Words
APPLICATIONS
Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique
shown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expanded
to any number of bits, see Table 1.
Table 1
WORD LENGTH
1 – 4 Bits
5 – 24 Bits
25 – 120 Bits
NUMBER OF PKGS.
1
2–6
8 – 31
INPUTS
(LSB)
A0 A1 A2 A3 B0 B1 B2 B3
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
#5
OA < B
IA < B
IA = B
OA = B
(MSB)
A20 A21 A22 A23 B20 B21 B22 B23
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
IA < B
#1
OA < B
IA = B
OA = B
NC
NOTE:
The SN54/74LS85 can be used as a 5-bit comparator
only when the outputs are used to drive the A0–A3 and
B0–B3 inputs of another SN54/74LS85 as shown in
Figure 2 in positions #1, 2, 3, and 4.
L
L
H
A19
B19
L
INPUTS
A5 A6 A7 A8 B5 B6 B7 B8
A0 A1 A2 A3 B0 B1 B2 B3
OA > B
IA > B
#4
IA < B
OA < B
IA = B
OA = B
A10 A11 A12 A13 B10 B11 B12 B13
A0 A1 A2 A3 B0 B1 B2 B3
OA > B
IA > B
#3
OA < B
IA < B
IA = B
OA = B
A15 A16 A17 A18 B15 B16 B17 B18
A0 A1 A2 A3 B0 B1 B2 B3
OA > B
IA > B
#2
OA < B
IA < B
IA = B
OA = B
A4
B4
L
A9
B9
NC
L
A14
B14
NC
L
NC
A0 A1 A2 A3 B0 B1 B2 B3
IA > B
OA > B
IA < B
OA < B
#6
IA = B
OA = B
OUTPUTS
MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNIFICANT BIT
L = LOW LEVEL
H = HIGH LEVEL
NC = NO CONNECTION
Figure 2. Comparison of Two 24-Bit Words
FAST AND LS TTL DATA
5-86
SN54/74LS85
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
A < B, A > B
Other Inputs
A < B, A > B
Other Inputs
IIL
IOS
ICC
Input LOW Current
A < B, A > B
Other Inputs
Output Short Circuit Current (Note 1)
Power Supply Current
– 20
0.35
0.5
V
µA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH
20
60
0.1
0.3
– 0.4
– 1.2
–100
20
VCC = MAX, VIN = 2.7 V
mA
VCC = MAX, VIN = 7.0 V
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Any A or B to A < B, A > B
Any A or B to A = B
A < B or A = B to A > B
A = B to A = B
A > B or A = B to A < B
Min
Typ
24
20
27
23
14
11
13
13
14
11
Max
36
30
45
45
22
17
20
26
22
17
Unit
ns
ns
ns
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC WAVEFORMS
VIN
1.3 V
tPHL
1.3 V
tPLH
1.3 V
VIN
1.3 V
tPHL
1.3 V
tPLH
1.3 V
VOUT
1.3 V
VOUT
1.3 V
Figure 3
Figure 4
FAST AND LS TTL DATA
5-87
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