FM25040B
4Kb Serial 5V F-RAM Memory
Features
4K bit Ferroelectric Nonvolatile RAM
Organized as 512 x 8 bits
High Endurance 1 Trillion (10
12
) Read/Writes
38 year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 20 MHz maximum Bus Frequency
Direct hardware replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Sophisticated Write Protection Scheme
Hardware Protection
Software Protection
Low Power Consumption
250 A Active Current (1 MHz)
4 A (typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC (-G)
Description
The FM25040B is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 38 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
The FM25040B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM25040B is capable of
supporting up to 10
12
read/write cycles, or a million
times more write cycles than EEPROM.
These capabilities make the FM25040B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25040B provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25040B uses the high-speed
SPI bus, which enhances the high-speed write
capability of F-RAM technology. The specifications
are guaranteed over an industrial temperature range
of -40°C to +85°C.
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VDD
HOLD
SCK
SI
Pin Names
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage 5V
Ground
Ordering Information
FM25040B-G
“Green” 8-pin SOIC
FM25040B-GTR
“Green” 8-pin SOIC,
Tape & Reel
This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s
internal qualification testing and has reached production status.
Cypress Semiconductor Corporation
•
Document Number: 001-86145 Rev. *A
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600
Revised March 07, 2013
FM25040B - 4Kb 5V SPI F-RAM
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
64 x 64
FRAM Array
Instruction Register
Address Register
Counter
SI
9
8
Data I/O Register
2
Nonvolatile Status
Register
SO
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
Description
Chip Select. This active-low input activates the device. When high, the device enters low-
power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the
device internally activates the SCK signal. A falling edge on /CS must occur prior to every
op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the
rising edge and outputs occur on the falling edge. Since the device is static, the clock
frequency may be any value between 0 and 20 MHz and may be interrupted at any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for
another task. When /HOLD is low, the current operation is suspended. The device ignores
any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low.
Write Protect: This active-low pin prevents all write operations, including those to the
status register. If high, write access is determined by the other write protection features, as
controlled through the status register. A complete explanation of write protection is
provided on page 6.
Serial Input: All input data is driven to this pin. The pin is sampled on the rising edge of
SCK and is ignored at other times. It should always be driven to a valid logic level to meet
I
DD
specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: SO is the data output pin. It is driven actively during a read and remains tri-
state at all other times including when /HOLD is low. Data transitions are driven on the
falling edge of the serial clock.
* SO can be connected to SI for a single pin data interface since the part communicates in
half-duplex fashion.
Supply Voltage: 5V
Ground
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Document Number: 001-86145 Rev. *A
Page 2 of 14
FM25040B - 4Kb 5V SPI F-RAM
Overview
The FM25040B is a serial F-RAM memory. The
memory array is logically organized as 512 x 8 and is
accessed using an industry standard Serial Peripheral
Interface or SPI bus. Functional operation of the F-
RAM is similar to serial EEPROMs. The major
difference between the FM25040B and a serial
EEPROM with the same pin-out relates to its
superior write performance. This makes the
FM25040B a drop-in replacement for most 4Kb SPI
EEPROMs that support Modes 0 & 3.
Serial Peripheral Interface – SPI Bus
The FM25040B employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to 20
MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25040B operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25040B devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25040B device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the /HOLD pin. Figure 3 shows a
configuration that uses only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25040B will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25040B supports Modes 0 and 3. Figure 4 shows
the required signal relationships for Modes 0 and 3.
For both modes, data is clocked into the FM25040B
on the rising edge of SCK and data is expected on the
first rising edge after /CS goes active. If the clock
begins from a high state, it will fall prior to beginning
data transfer in order to create the first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After /CS
is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Important: The /CS must go inactive (high) after
an operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Memory Architecture
When accessing the FM25040B, the user addresses
512 locations each with 8 data bits. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code
including the upper address bit, and a word address.
The word address consists of the lower 8-address
bits. The complete address of 9-bits specifies each
byte address uniquely.
Most functions of the FM25040B either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation essentially is zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation will be
complete. This is explained in more detail in the
interface section that follows.
Users expect several obvious system benefits from
the FM25040B due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM25040B contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that V
DD
is within datasheet tolerances to
prevent incorrect operation. It is recommended
that the part is not powered down with chip
enable active.
Document Number: 001-86145 Rev. *A
Page 3 of 14
FM25040B - 4Kb 5V SPI F-RAM
SCK
MOSI
MISO
SO
SI SCK
SO
SI SCK
SPI
Microcontroller
SS1
SS2
HOLD1
HOLD2
MOSI: Master Out, Slave In
MISO: Master In, Slave Out
SS: Slave Select
FM25040B
CS
HOLD
FM25040B
CS
HOLD
Figure 2. System Configuration with SPI port
Microcontroller
SO
SI SCK
FM25040B
CS
HOLD
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Document Number: 001-86145 Rev. *A
Page 4 of 14
FM25040B - 4Kb 5V SPI F-RAM
Data Transfer
All data transfers to and from the FM25040B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. The serial input data is clocked in on
the rising edge of SCK. The serial data output is
driven from the falling edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25040B. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent data transfer.
They perform a single function, such as, enabling a
write operation. Second are commands followed by
one byte, either in or out. They operate on the status
register. Third are commands for memory
transactions followed by address and one or more
bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE
Write Memory Data
WREN - Set Write Enable Latch
The FM25040B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted. A write
to the status register has no effect on the WEL bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Op-code
0000_0110b
0000_0100b
0000_0101b
0000_0001b
0000_A011b
0000_A010b
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Document Number: 001-86145 Rev. *A
Page 5 of 14
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