FM23MLD16
8Mbit F-RAM Memory
Features
8Mbit Ferroelectric Nonvolatile RAM
•
Organized as 512Kx16
•
Configurable as 1Mx8 Using /UB, /LB
•
High Endurance 100 Trillion (10
14
) Read/Writes
•
NoDelay™ Writes
•
Page Mode Operation to 33MHz
•
Advanced High-Reliability Ferroelectric Process
SRAM Compatible
•
JEDEC 512Kx16 SRAM Pinout
•
60 ns Access Time, 115 ns Cycle Time
Advanced Features
•
Low V
DD
Monitor Protects Memory against
Inadvertent Writes
Superior to Battery-backed SRAM Modules
•
No Battery Concerns
•
Monolithic Reliability
•
True Surface Mount Solution, No Rework Steps
•
Superior for Moisture, Shock, and Vibration
Low Power Operation
•
2.7V – 3.6V Power Supply
•
14 mA Active Current
Industry Standard Configuration
•
Industrial Temperature -40° C to +85° C
•
48-pin “Green”/RoHS FBGA package
Description
The FM23MLD16 is a 512Kx16 nonvolatile memory
that reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and very high write endurance
make F-RAM superior to other types of memory.
In-system operation of the FM23MLD16 is very
similar to other RAM devices and can be used as a
drop-in replacement for standard SRAM. Read and
write cycles may be triggered by a chip enable or
simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric
memory process. These features make the
FM23MLD16 ideal for nonvolatile memory
applications requiring frequent or rapid writes in the
form of an SRAM.
The FM23MLD16 includes a low voltage monitor
that blocks access to the memory array when V
DD
drops below a critical threshold. The memory is
protected against an inadvertent access and data
corruption under this condition.
The FM23MLD16 F-RAM is available in a 48-ball
FBGA surface mount package. Device specifications
are guaranteed over the industrial temperature range
of –40°C to +85°C.
48-Ball FBGA Top View (Ball Down)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
/LB
/OE
A0
A1
A2
CE2
DQ8
/UB
A3
A4
/CE1
DQ0
DQ9
DQ10
A5
A6
DQ1
DQ2
VSS
DQ11
A17
A7
DQ3
VDD
VDD
DQ12
NC
A16
DQ4
VSS
DQ14
DQ13
A14
A15
DQ5
DQ6
DQ15
NC
A12
A13
/WE
DQ7
A18
A8
A9
A10
A11
NC
Ordering Information
FM23MLD16-60-BG 60 ns access, 48-pin
“Green”/RoHS FBGA
This product conforms to the specifications per the terms of the Ramtron standard warranty.
The product has completed Ramtron’s internal qualification testing and has reached
production status.
Rev. 2.0
June 2012
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 13
FM23MLD16 - 512Kx16 FRAM (multi die)
Address Latch
Chip & Row Decoder
A(18:0)
A(18:2)
64K x 64
64K x 64
F-RAM Array
A(1:0)
CE1, CE2
WE
UB, LB
OE
2
Column Decoder
2
Control
Logic
I/O Latch & Bus Driver
DQ(15:0)
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(18:0)
Input
/CE1, CE2
Input
/WE
Input
/OE
DQ(15:0)
/UB
/LB
VDD
VSS
Input
I/O
Input
Input
Supply
Supply
Pin Description
Address inputs: The A(17:0) address lines select one of 262,144 words in each of the F-
RAM die. A18 selects one of the two die. The lowest two address lines A(1:0) may be
used for page mode read and write operations.
Chip Enable inputs: The device is selected and a new memory access begins on the
falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The
entire address is latched internally at this point.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM23MLD16 to write the data on the DQ bus to the F-RAM array. The falling edge of
/WE latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM23MLD16 drives the data bus when valid read
data is available. Deasserting /OE high tri-states the DQ pins.
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z
if /UB is high.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
Supply Voltage: 3.3V
Ground
Rev. 2.0
June 2012
Page 2 of 13
FM23MLD16 - 512Kx16 FRAM (multi die)
Functional Truth Table
1
/CE1
CE2
/WE
H
X
X
X
L
X
H
H
↓
H
L
↑
L
H
H
L
H
H
H
L
↓
L
L
↑
L
H
↓
L
H
↓
H
X
↑
X
L
↓
Notes:
1)
2)
3)
4)
A(18:2)
X
X
V
V
No Change
Change
V
V
V
No Change
X
X
A(1:0)
X
X
V
V
Change
V
V
V
V
V
X
X
Operation
Standby/Idle
Read
Page Mode Read
Random Read
/CE-Controlled Write
2
/WE-Controlled Write
2, 3
Page Mode Write
4
Starts Precharge
H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.
For write cycles, data-in is latched on the rising edge of /CE1 or /WE of the falling edge of CE2, whichever comes first.
/WE-controlled write cycle begins as a Read cycle and A(18:3) is latched then.
Addresses A(2:0) must remain stable for at least 15 ns during page mode operation.
Byte Select Truth Table
/OE
/LB
/UB
H
X
X
X
H
H
L
H
L
L
H
L
L
X
H
L
L
H
L
L
Operation
Read; Outputs Disabled
Read; DQ(7:0) Hi-Z
Read; DQ(15:8) Hi-Z
Read
Write; Mask DQ(7:0)
Write; Mask DQ(15:8)
Write
Rev. 2.0
June 2012
Page 3 of 13
FM23MLD16 - 512Kx16 FRAM (multi die)
Overview
The FM23MLD16 is a wordwide F-RAM memory
logically organized as 524,288 x 16 and accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page is triggered
by toggling a chip enable pin or simply by changing
the upper address A(18:2).
Write Operation
Writes occur in the FM23MLD16 in the same time
interval as reads. The FM23MLD16 supports both
/CE- and /WE-controlled write cycles. In both cases,
the address A(18:2) is latched on the falling edge of
/CE1 (while CE2 high) or the rising edge of CE2
(while /CE1 low).
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when the device is activated with a chip enable.
In this case, the device begins the memory cycle as a
write. The FM23MLD16 will not drive the data bus
regardless of the state of /OE as long as /WE is low.
Input data must be valid when the device is
deselected with a chip enable. In a /WE-controlled
write, the memory cycle begins when the device is
activated with a chip enable. The /WE signal falls
some time later. Therefore, the memory cycle begins
as a read. The data bus will be driven if /OE is low,
however it will hi-Z once /WE is asserted low. The
/CE- and /WE-controlled write timing cases are
shown in the Electrical Specifications section. In the
Write Cycle Timing 2
diagram, the data bus is shown
as a hi-Z condition while the chip is write-enabled
and before the required setup time. Although this is
drawn to look like a mid-level voltage, it is
recommended that all DQ pins comply with the
minimum V
IH
/V
IL
operating levels.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the deassertion of /WE, /CE1, or
CE2, whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE, /CE1, or CE2. Data setup
time indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or the chip is deselected with /CE1 or
CE2).
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The FM23MLD16 provides the user fast access to
any data within a row element. Each row has 4
column address locations. Address inputs A(1:0)
define the column address to be accessed. An access
can start on any column address, and other column
Page 4 of 13
Memory Operation
Users access 524,288 memory locations, each with
16 data bits through a parallel interface. The F-RAM
memory is organized as 2 die each having 64K rows.
Each row has 4 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE1
(while CE2 high) or the rising edge of CE2 (while
/CE1 low), subsequent column locations may be
accessed without the need to toggle a chip enable.
When either chip enable pin is deasserted, a
precharge
operation
begins.
Writes
occur
immediately at the end of the access with no delay.
The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to F-RAM called NoDelay
TM
writes.
Read Operation
A read operation begins on the falling edge of /CE1
(while CE2 high) or the rising edge of CE2 (while
/CE1 low). The /CE-initiated access causes the
address to be latched and starts a memory read cycle
if /WE is high. Data becomes available on the bus
after the access time has been satisfied. Once the
address has been latched and the access completed, a
new access to a random location (different row) may
begin while both chip enables are still active. The
minimum cycle time for random addresses is t
RC
.
Note that unlike SRAMs, the FM23MLD16’s /CE-
initiated access time is faster than the address cycle
time.
The FM23MLD16 will drive the data bus when /OE
and at least one of the byte enables (/UB, /LB) is
asserted low. The upper data byte is driven when /UB
is low, and the lower data byte is driven when /LB is
low. If /OE is asserted after the memory access time
has been satisfied, the data bus will be driven with
valid data. If /OE is asserted prior to completion of
the memory access, the data bus will not be driven
until valid data is available. This feature minimizes
supply current in the system by eliminating transients
caused by invalid data being driven onto the bus.
When /OE is deasserted high, the data bus will
remain in a high-Z state.
Rev. 2.0
June 2012
FM23MLD16 - 512Kx16 FRAM (multi die)
locations may be accessed without the need to toggle
the CE pins. For fast access reads, once the first data
byte is driven onto the bus, the column address inputs
A(1:0) may be changed to a new value. A new data
byte is then driven to the DQ pins no later than t
AAP
,
which is less than half the initial read access time.
For fast access writes, the first write pulse defines the
first write access. While the device is selected (both
chip enables asserted), a subsequent write pulse along
with a new column address provides a page mode
write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving at
least one of the chip enable signals to an inactive
state. It must remain high for at least the minimum
precharge time t
PC
.
For applications that require the lowest power
consumption, the /CE1 signal should be active only
during memory accesses. The FM23MLD16 draws
supply current while /CE1 is low, even if addresses
and control signals are static. While /CE1 is high, the
device draws no more than the maximum standby
current I
SB
.
Note that if /CE1 is grounded and CE2 tied to V
DD
,
the user must be sure /WE is not low at powerup or
powerdown events. If the chip is enabled and /WE is
low during power cycles, data corruption will occur.
Figure 3 shows a pullup resistor on /WE which will
keep the pin high during power cycles assuming the
MCU/MPU pin tri-states during the reset condition.
The pullup resistor value should be chosen to ensure
the /WE pin tracks V
DD
yet a high enough value that
the current drawn when /WE is low is not an issue. A
10Kohm resistor draws 330uA when /WE is low and
V
DD
=3.3V.
V
DD
R
MCU/
MPU
FM23MLD16
CE2
CE1
WE
OE
A(18:0)
DQ(15:0)
SRAM Drop-In Replacement
The FM23MLD16 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require the CE pins to toggle for each
new address. Both CE pins may remain active
indefinitely. When both CE pins are active, the
device automatically detects address changes and a
new access is begun. This functionality allows the
chip enable pins to be tied active (/CE1 grounded,
CE2 tied to V
DD
) as you might with an SRAM. It also
allows page mode operation at speeds up to 33MHz.
A typical application is shown in Figure 2. It shows a
pullup resistor on /CE1 which will keep the pin high
during power cycles assuming the MCU/MPU pin tri-
states during the reset condition. The pullup resistor
value should be chosen to ensure the /CE1 pin tracks
V
DD
yet a high enough value that the current drawn
when /CE1 is low is not an issue. Although not
required, it is recommended that CE2 be tied to V
DD
if the controller provides an active-low chip enable.
V
DD
FM23MLD16
R
CE2
CE1
Figure 3. Use of Pullup Resistor on /WE
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 1Mx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(19) may be
available from the system processor.
MCU/
MPU
WE
OE
A(18:0)
DQ(15:0)
Figure 2. Typical Application using Pullup
Resistor on /CE1
Rev. 2.0
June 2012
Figure 4. FM23MLD16 Wired as 1Mx8
Page 5 of 13
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