Preliminary
FM20L08
1Mbit Bytewide FRAM Memory – Extended Temp.
Features
1Mbit Ferroelectric Nonvolatile RAM
•
Organized as 128Kx8
•
Unlimited Read/Write Cycles
•
NoDelay™ Writes
•
Page Mode Operation to 33MHz
•
Advanced High-Reliability Ferroelectric Process
SRAM Replacement
•
JEDEC 128Kx8 SRAM pinout
•
60 ns Access Time, 350 ns Cycle Time
System Supervisor
•
Low Voltage monitor drives external /LVL signal
•
Write protects memory for low voltage condition
•
Software programmable block write protect
Superior to Battery-backed SRAM Modules
•
No battery concerns
•
Monolithic reliability
•
True surface mount solution, no rework steps
•
Superior for moisture, shock, and vibration
•
Resistant to negative voltage undershoots
Low Power Operation
•
3.3V +10%, -5% Power Supply
•
22 mA Active Current
Industry Standard Configurations
•
Extended Temperature -25° C to +85° C
•
32-pin “green” TSOP (-TG)
Description
The FM20L08 is a 128K x 8 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and unlimited write endurance make
FRAM superior to other types of memory.
In-system operation of the FM20L08 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM20L08 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM20L08 includes a voltage monitor function
that monitors the power supply voltage. It asserts an
active-low signal that indicates the memory is write-
protected when V
DD
drops below a critical threshold.
When the /LVL signal is low, the memory is
protected against an inadvertent access and data
corruption.
The FM20L08 also features software-controlled write
protection. The memory array is divided into 8
uniform blocks, each of which can be individually
write protected.
Device specifications are guaranteed over the
temperature range -25°C to +85°C.
Pin Configuration
A11
A9
A8
A13
WE
DNU
A15
VDD
LVL
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Ordering Information
FM20L08-60-TG
60 ns access, 32-pin
“Green” TSOP
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.4
Oct. 2005
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Page 1 of 14
FM20L08 - Extended Temp.
16K x 8 block
16K x 8 block
Block & Row Decoder
Address Latch
16K x 8 block
16K x 8 block
A(16:0)
...
16K x 8 block
A(16:3)
16K x 8 block
A(2:0)
16K x 8 block
16K x 8 block
...
Column Decoder
CE
WE
OE
Control
Logic
I/O Latch & Bus Driver
DQ(7:0)
VDD
LVL
VDD Monitor
Write
Protect
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(16:0)
Input
/CE
Input
/WE
Input
/OE
DQ(7:0)
/LVL
Input
I/O
Output
DNU
VDD
VSS
-
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 bytes in the FRAM array.
The address value is latched on the falling edge of /CE. Addresses A(2:0) are used for
page mode read and write operations.
Chip Enable inputs: The device is selected and a new memory access begins when /CE
is low. The entire address is latched internally on the falling edge of chip enable.
Subsequent changes to the A(2:0) address inputs allow page mode operation.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM20L08 to write the data on the DQ bus to the FRAM array. The falling edge of /WE
latches a new column address for fast page mode write cycles.
Output Enable: When /OE is low, the FM20L08 drives the data bus when valid data is
available. Deasserting /OE high tri-states the DQ pins.
Data: 8-bit bi-directional data bus for accessing the FRAM array.
Low Voltage Lockout: When the voltage monitor detects that V
DD
is below V
TP
, the
/LVL pin will be asserted low. While /LVL is low, the memory array cannot be accessed
which prevents a low voltage write from corrupting data. When V
DD
is within its normal
operating limits, the /LVL signal will be pulled high.
Do Not Use: This pin should be left unconnected.
Supply Voltage: 3.3V
Ground
Rev. 1.4
Oct. 2005
Page 2 of 14
FM20L08 - Extended Temp.
Functional Truth Table
/CE
/WE
H
X
H
↓
L
H
L
H
L
↓
L
↓
L
↓
X
↑
Notes:
1)
2)
3)
4)
A(16:3)
X
V
No Change
Change
V
X
No Change
X
A(2:0)
X
V
Change
V
V
V
V
X
Operation
Standby/Idle
Read
Page Mode Read
Random Read
/CE-Controlled Write
/WE-Controlled Write
2
Page Mode Write
3
Starts Precharge
H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care.
/WE-controlled write cycle begins as a Read cycle and A(16:3) is latched then.
Addresses A(2:0) must remain stable for at least 15 ns during page mode operation.
For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
Rev. 1.4
Oct. 2005
Page 3 of 14
FM20L08 - Extended Temp.
Overview
The FM20L08 is a bytewide FRAM memory
logically organized as 131,072 x 8 and is accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(16:3) changes.
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is deasserted high. In a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown on page 11. In the
Write
Cycle Timing 2
diagram, the data bus is shown as a
hi-Z condition while the chip is write-enabled and
before the required setup time. Although this is
drawn to look like a mid-level voltage, it is
recommended that all DQ pins comply with the
minimum V
IH
/V
IL
operating levels.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (/WE or
/CE high).
Unlike other truly nonvolatile memory technologies,
there is no write delay with FRAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The FM20L08 provides the user fast access to any
data within a row element. Each row has eight
column locations. An access can start anywhere
within a row and other column locations may be
accessed without the need to toggle the /CE pin. For
page mode reads, once the first data byte is driven
onto the bus, the column address inputs A(2:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins. For page mode writes, the
first write pulse defines the first write access. While
/CE is low, a subsequent write pulse along with a new
column address provides a page mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is prepared for a new
access. Precharge is user-initiated by driving the /CE
signal high. It must remain high for at least the
minimum precharge time t
PC
.
Memory Operation
Users access 131,072 memory locations with 8 data
bits each through a parallel interface. The FRAM
array is organized as 8 blocks each having 2048 rows.
Each row has 8 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is
deasserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the
FM20L08’s /CE-initiated access time is faster than
the address cycle time.
The FM20L08 will drive the data bus only when /OE
is asserted low and the memory access time has been
satisfied. If /OE is asserted prior to completion of the
memory access, the data bus will not be driven until
valid data is available. This feature minimizes supply
current in the system by eliminating transients caused
by invalid data being driven onto the bus. When /OE
is inactive, the data bus will remain hi-Z.
Write Operation
Writes occur in the FM20L08 in the same time
interval as reads. The FM20L08 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM20L08 will not
Rev. 1.4
Oct. 2005
Page 4 of 14
FM20L08 - Extended Temp.
Supply Voltage Monitor
An internal voltage monitor circuit continuously
checks the V
DD
supply voltage. When V
DD
is below
the specified threshold V
TP
, the monitor asserts the
/LVL signal to an active-low state. The FM20L08
locks out access to the memory when V
DD
is below
the trip voltage. This prevents the system from
accessing memory when V
DD
is too low and
inadvertently corrupting the data. The /LVL signal
should not be used as a system reset signal because
the system host may attempt to write data to the
FM20L08 below its specified operating voltage. The
/LVL pin may be used as a status indicator that the
memory is locked out.
On power up, the /LVL signal will begin in a low
state signifying that V
DD
is below the V
TP
threshold. It
will remain low as long as V
DD
is below that level.
Once V
DD
rises above V
TP
, a hold-off timer will begin
creating the delay t
PULV
. Once this delay has elapsed,
the /LVL signal will go high or inactive. At this time
the memory can be accessed. The memory is ready
for access prior to t
PU
as shown in the Electrical
Specifications section. The /LVL signal will remain
high until V
DD
drops below the threshold.
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
write address is ignored. Rather the byte will be held
pending the next cycle, which must be a write of the
data complement to the protection settings. If the
complement is correct, the write protect settings will
be updated. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector.
Setting a bit to 1 write protects the corresponding
sector; a 0 enables writes for that sector. The
following table shows the write-protect sectors with
the corresponding bit that controls the write-protect
setting.
Write Protect Sectors – 16K x8 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect address sequence follows:
1.
05555h *
2.
1AAAAh
3.
03333h
4.
1CCCCh
5.
100FFh
6.
0FF00h
7.
1AAAAh
8.
1CCCCh
9.
0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 05555h.
The address sequence provides a very secure way of
modifying the protection. The correct address
sequence has a 1 in 5 x 10
30
chance of occurring
accidentally. A flow chart of the entire write protect
operation is shown in Figure 2. As mentioned above,
write-protect settings are nonvolatile. The factory
default is unprotected.
Software Write Protection
The 128Kx8 address space is divided into 8 sectors
(blocks) of 16Kx8 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands and two write commands.
The specific sequence of read addresses must be
provided in order to access to the write protect mode.
Following the read address sequence, the host must
write a data byte that specifies the desired protection
state of each sector. For confirmation, the system
must then write the complement of the protection byte
immediately following the protection byte. Any error
that occurs including read addresses in the wrong
order, issuing a seventh read address, or failing to
complement the protection value will leave the write
protection unchanged.
The write-protect state machine monitors all
addresses, taking no action until the write-protect
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
Rev. 1.4
Oct. 2005
Page 5 of 14
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