Pre-Production
FM18W08
256Kb Wide Voltage Bytewide F-RAM
Features
256Kbit Ferroelectric Nonvolatile RAM
Organized as 32,768 x 8 bits
High Endurance 100 Trillion (10
14
) Read/Writes
38 year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Superior to BBSRAM Modules
No Battery Concerns
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
Resistant to Negative Voltage Undershoots
SRAM & EEPROM Compatible
JEDEC 32Kx8 SRAM & EEPROM pinout
70 ns Access Time
130 ns Cycle Time
Low Power Operation
Wide Voltage Operation 2.7V to 5.5V
12 mA Active Current
20
A
(typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40 C to +85 C
28-pin “Green”/RoHS SOIC Package
Description
The FM18W08 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile but operates in other respects as a RAM.
It provides data retention for 38 years while
eliminating the reliability concerns, functional
disadvantages and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing
and high write endurance make F-RAM superior to
other types of nonvolatile memory.
In-system operation of the FM18W08 is very similar
to other RAM devices. Minimum read- and write-
cycle times are equal. The F-RAM memory, however,
is nonvolatile due to its unique ferroelectric memory
process. Unlike BBSRAM, the FM18W08 is a truly
monolithic nonvolatile memory. It provides the same
functional benefits of a fast write without the
disadvantages associated with modules and batteries
or hybrid memory solutions.
These capabilities make the FM18W08 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in a bytewide environment. The
availability of a true surface-mount package improves
the manufacturability of new designs. Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Ordering Information
FM18W08-SG
28-pin “Green” SOIC
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change
the specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 2.0
Dec. 2011
Page 1 of 11
FM18W08
A(14:0)
Address
Latch &
Decoder
A(14:0)
32,768 x 8 FRAM Array
CE
WE
OE
Control
Logic
I/O Latch
Bus Driver
DQ(7:0)
Figure 1. Block Diagram
Pin Description
Pin Name
A(14:0)
DQ(7:0)
/CE
Type
Input
I/O
Input
/OE
Input
/WE
VDD
VSS
Input
Supply
Supply
Description
Address: The 15 address lines select one of 32,768 bytes in the F-RAM array. The
address value is latched on the falling edge of /CE.
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs.
Output Enable: Asserting /OE low causes the FM18W08 to drive the data bus
when valid data is available. Deasserting /OE high causes the DQ pins to be tri-
stated.
Write Enable: Asserting /WE low causes the FM18W08 to write the contents of
the data bus to the address location latched by the falling edge of /CE.
Supply Voltage
Ground
Functional Truth Table
/CE
/WE
H
X
X
L
H
L
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
Write
Note: The /OE pin controls only the DQ output buffers.
Rev. 2.0
Dec. 2011
Page 2 of 11
FM18W08
Overview
The FM18W08 is a bytewide F-RAM memory. The
memory array is logically organized as 32,768 x 8
and is accessed using an industry standard parallel
interface. All data written to the part is immediately
nonvolatile with no delay. Functional operation of the
F-RAM memory is the same as SRAM type devices,
except the FM18W08 requires a falling edge of /CE
to start each memory cycle.
/CE goes inactive. Data becomes available on the bus
after the access time has been satisfied.
After the address has been latched, the address value
may be changed upon satisfying the hold time
parameter. Unlike an SRAM, changing address values
will have no effect on the memory operation after the
address is latched.
The FM18W08 will drive the data bus when /OE is
asserted low. If /OE is asserted after the memory
access time has been satisfied, the data bus will be
driven with valid data. If /OE is asserted prior to
completion of the memory access, the data bus will
not be driven until valid data is available. This feature
minimizes supply current in the system by eliminating
transients caused by invalid data being driven onto
the bus. When /OE is inactive the data bus will
remain tri-stated.
Write Operation
Writes occur in the FM18W08 in the same time
interval as reads. The FM18W08 supports both /CE-
and /WE-controlled write cycles. In all cases, the
address is latched on the falling edge of /CE.
In a /CE controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the part begins the
memory cycle as a write. The FM18W08 will not
drive the data bus regardless of the state of /OE.
In a /WE controlled write, the memory cycle begins
on the falling edge of /CE. The /WE signal falls after
the falling edge of /CE. Therefore, the memory cycle
begins as a read. The data bus will be driven
according to the state of /OE until /WE falls. The
timing of both /CE- and /WE-controlled write cycles
is shown in the electrical specifications.
Write access to the array begins asynchronously after
the memory cycle is initiated. The write access
terminates on the rising edge of /WE or /CE,
whichever is first. Data set-up time, as shown in the
electrical specifications, indicates the interval during
which data cannot change prior to the end of the write
access.
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Therefore, any operation including read or
write can occur immediately following a write. Data
polling, a technique used with EEPROMs to
determine if a write is complete, is unnecessary.
Page 3 of 11
Memory Architecture
Users access 32,768 memory locations each with 8
data bits through a parallel interface. The complete
15-bit address specifies each of the 32,768 bytes
uniquely. Internally, the memory array is organized
into 4092 rows of 8-bytes each. This block
segmentation has no effect on operation, however the
user may wish to group data into blocks by its
endurance characteristics as explained on page 4.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic
and timing circuits. Likewise the access time is the
same for read and write memory operations. When
/CE is deasserted high, a precharge operation begins,
and is required of every memory cycle. Thus unlike
SRAM, the access and cycle times are not equal.
Writes occur immediately at the end of the access
with no delay. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed.
It is the user’s responsibility to ensure that V
DD
remains within datasheet tolerances to prevent
incorrect operation. Also proper voltage level and
timing relationships between V
DD
and /CE must be
maintained during power-up and power-down events.
See Power Cycle Timing diagram on page 9.
Memory Operation
The FM18W08 is designed to operate in a manner
similar to other bytewide memory products. For users
familiar with BBSRAM, the performance is
comparable but the bytewide interface operates in a
slightly different manner as described below. For
users familiar with EEPROM, the obvious differences
result from the higher write performance of F-RAM
technology including NoDelay writes and much
higher write endurance.
Read Operation
A read operation begins on the falling edge of /CE.
At this time, the address bits are latched and a
memory cycle is initiated. Once started, a full
memory cycle must be completed internally even if
Rev. 2.0
Dec. 2011
FM18W08
Precharge Operation
The precharge operation is an internal condition that
prepares the memory for a new access. All memory
cycles consist of a memory access and a precharge.
The precharge is initiated by deasserting the /CE pin
high. It must remain high for at least the minimum
precharge time t
PC
.
The user determines the beginning of this operation
since a precharge will not begin until /CE rises.
However, the device has a maximum /CE low time
specification that must be satisfied.
150,000 accesses per second to the same row for over
20 years.
F-RAM Design Considerations
When designing with F-RAM for the first time, users
of SRAM will recognize a few minor differences.
First, bytewide F-RAM memories latch each address
on the falling edge of chip enable. This allows the
address bus to change after starting the memory
access. Since every access latches the memory
address on the falling edge of /CE, users cannot
ground it as they might with SRAM.
Users who are modifying existing designs to use F-
RAM should examine the memory controller for
timing compatibility of address and control pins.
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change required. An example of the signal
relationships is shown in Figure 2 below. Also shown
is a common SRAM signal relationship that will not
work for the FM18W08.
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle
involves a change of state. The memory architecture
is based on an array of rows and columns. Each read
or write access causes an endurance cycle for an
entire row. In the FM18W08, a row is 64 bits wide.
Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring
frequently accessed data is located in different rows.
Regardless, F-RAM offers substantially higher write
endurance than other nonvolatile memories. The
rated endurance limit of 10
14
cycles will allow
Valid Strobing of /CE
CE
FRAM
Signaling
Address
A1
A2
Data
D1
D2
Invalid Strobing of /CE
CE
SRAM
Signaling
Address
A1
A2
Data
D1
D2
Figure 2. Chip Enable and Memory Address Relationships
Rev. 2.0
Dec. 2011
Page 4 of 11
FM18W08
A second design consideration relates to the level of
V
DD
during operation. Battery-backed SRAMs are
forced to monitor V
DD
in order to switch to battery
backup. They typically block user access below a
certain V
DD
level in order to prevent loading the
battery with current demand from an active SRAM.
The user can be abruptly cut off from access to the
nonvolatile memory in a power down situation with
no warning or indication.
F-RAM memories do not need this system overhead.
The memory will not block access at any V
DD
level
that complies with the specified operating range. The
user should take measures to prevent the processor
from accessing memory when V
DD
is out-of-
tolerance. The common design practice of holding a
processor in reset during powerdown may be
sufficient. It is recommended that Chip Enable is
pulled high and allowed to track V
DD
during powerup
and powerdown cycles. It is the user’s responsibility
to ensure that chip enable is high to prevent accesses
below V
DD
min. (2.7V). Figure 3 shows a pullup
resistor on /CE which will keep the pin high during
power cycles assuming the MCU/MPU pin tri-states
during the reset condition. The pullup resistor value
should be chosen to ensure the /CE pin tracks V
DD
yet
a high enough value that the current drawn when /CE
is low is not an issue.
V
DD
R
FM18W08
CE
MCU/
MPU
WE
OE
A(14:0)
DQ
Figure 3. Use of Pullup Resistor on /CE
Rev. 2.0
Dec. 2011
Page 5 of 11
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