µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
October 2009
FIN224C
24-Bit Low-Power Serializer/Deserializer
Features
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Dynamic Current
Standby Current
Core Voltage (V
DDA/S
)
I/O Voltage (V
DDP
)
ESD
Package
Ordering Information
24
20MHz
HVGA
Microcontroller / RGB
I86 & m68
17mA at 10Mhz
10µA
2.5V to 3.3V
1.65V to 3.6V
15KV (IEC)
MLP-40 (6 x 6mm)
FIN224CMLX, MLP-40
Description
The FIN224C
μSerDes™
is a low-power serializer/
deserializer (μSerDes™) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred from
one point to another can be significantly reduced. Typical
reduction is 5:1 for unidirectional paths. Through the use of
differential signaling, shielding and EMI filters can also be
minimized, further reducing the cost of serialization.
The differential signaling is also important for providing a
noise-insensitive signal that can withstand radio and
electrical noise sources. Major reduction in power
consumption allows minimal impact on battery life in mobile
applications. It is possible to use a single Phase-Locked Loop
(PLL) for most applications, including bi-directional operation.
Related Resources
For samples and questions, please contact:
interface@fairchildsemi.com.
Applications
Slider, Folder, and Clamshell Mobile Handsets
GSM and CDMA Phones
Typical Application
Simple Interface
Built-in voltage
translation
Serializer
+
-
+
-
70-130
Ohms
2
2
Deserializer
24-Bit Deserializer
+
-
+
-
24-Bit Serializer
24-Bit Serializer
Baseband
Main
Display
Internal
Termination
Figure 1. Mobile Phone Example
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Pin Configuration
Pin Name
STROBE
CKREF
CKP
DP[24:1]
/DIRO
S1, S2
DIRI
DSO+ / DSI-
DSO- / DSI+
CKSI+, CKSI-
CKSO+, CKSO-
VDDP
VDDS
VDDA
GND
Description
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
LVCMOS Clock Input and PLL Reference
LVCMOS Word Clock Output
LVCMOS Data I/O
LVCMOS Control Output Inversion of DIRI
LVCMOS Select Pins, Controls the Mode of Operation,
see Table 1
LVCMOS Control, Selects Serializer or Deserializer Mode
Serial Data I/O
Serial Clock Input
Serial Clock Output
Power Supply for Parallel I/O and Internal Circuitry
Power Supply for Serial I/O
Power Supply for Core
Ground Pins
0 Deserializer
1 Serializer
Note:
1. 0 = V
IL
; 1 = V
IH
.
32 STROBE
31 CKREF
30 /DIRO
29 CKSO+
28 CKSO-
27 DSO+ / DSI-
26 DSO- / DSI+
25 CKSI-
24 CKSI+
23 DIRI
22 S2
21 VDDS
S1 19
VDDA 20
35 DP[3]
DP[22] 16
34 DP[2]
DP[23] 17
36 DP[4]
DP[9] 1
DP[10] 2
DP[11] 3
DP[12] 4
VDDP 5
CKP 6
DP[13] 7
DP[14] 8
DP[15] 9
DP[16] 10
DP[18] 12
DP[20] 14
DP[21] 15
DP[19] 13
DP[17] 11
DP[24] 18
GND PAD
Must be Grounded
Figure 2. MLP-40 Pinout (Through View)
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
33 DP[1]
40 DP[8]
39 DP[7]
38 DP[6]
37 DP[5]
www.fairchildsemi.com
2
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Table 1.
DIRI
Serializer / Deserializer, Operation, and Reset Modes
S1
S2
Reset Mode
Mode of Operation
X
0
0
LVCMOS Outputs = High Impedance
LVCMOS Inputs = Known State
1
0
0
1
1
0
Serializer Mode
Deserializer Mode
Application Diagrams
Serializer
FIN224C
Baseband
Processor
PCLK
1.8V
2.8V
Deserializer
FIN224C
2.8V
2.8V
Main Display
18-Bit RGB
PCLK
DATA[17:0]
HSYNC
VSYNC
/CS
RESET
VDDP VDDS/A
CKREF
STROBE
CKSO+
DP[18:1]
CKSO-
DP[19]
DP[20]
DSO+/DSI-
DP[21]
DSO-/DSI+
DP[24:22]
S1
S2
DIRI
/DIRO
CKP
CKSI+
CKSI-
VDDP VDDS/A
CKP
DP[18:1]
DP[19]
DP[20]
DP[21]
DSO-/DSI+
DSO+/DSI- DP[24:22]
CKSI+
CKSI-
CKSO+
CKSO-
DP[17:0]
HSYNC
VSYNC
/CS
Reset
GND
GND
S1
S2
DIRI
/DIRO
CKREF
STROBE
Figure 3. 18-Bit RGB Interface Block Diagram
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
3
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Clock
Source
Baseband
Processor
Serializer
FIN224C
1.8V
2.8V
Deserializer
FIN224C
2.8V
2.8V
Main Display
16-Bit µController
/WE
DATA[7:0]
DATA[15:8]
A0
/CS0
Main Display
8-Bit µController
/WE
DATA[7:0]
A0
/CS1
VDDP VDDS/A
CKREF
STROBE
DP[8:1]
DP[
DP[16:9]
DP
DP[17]
DP
DSO+/DSI-
DP[18]
DP[
DSO-/DSI+
DP
DP[19]
DP[24:
DP[24:20]
CKSI+
CKSI-
S1
S2
DIRI
GND
/DIRO
CKP
CKSO+
CKSO-
VDDP VDDS/A
CKP
DP
DP[8:1]
DP[:
DP[16:9]
DP[17]
DP
DP
DP[18]
DSO-/DSI+
DP
DP[19]
DSO+/DSI-
DP:
DP[24:20]
CKSI+
CKSI-
CKSO+
CKSO-
S1
S2
DIRI
/DIRO
CKREF
STROBE
/WE
DP[7:0]
DP[15:8]
A0
/CS0
/CS1
Reset
GND
Figure 4. Dual-Display µController Interface Block Diagram
Additional Application Information
Flex Cabling:
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O
flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
Keep all four differential serial wires the same length.
Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.
Design goal of 70 to 130Ω differential characteristic impedance.
Do not place test points on differential serial wires.
Design differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at
http://www.fairchildsemi.com/products/interface/userdes.html,
contact your sales
representative, or contact Fairchild directly at
interface@fairchildsemi.com
for applications notes or flex guidelines.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
4
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
V
DD
T
STG
T
J
T
L
Supply Voltage
All Input/Output Voltage
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature (Soldering, 4 Seconds)
IEC 61000 Board Level
ESD
All Pins
Human Body Model, JESD22-A114
Serial I/0, /RES, PAR/SPI to GND
8.0
Parameter
Min.
-0.5
-0.5
-65
Max.
+4.6
+4.6
+150
+150
+260
15.0
2.5
Unit
V
V
°C
°C
°C
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
V
DDA
, V
DDS(1)
V
DDP
T
A
Supply Voltage
Supply Voltage
Operating Temperature
Parameter
Min.
2.5
1.65
-30
Max.
3.3
3.60
+70
Unit
V
V
°C
Note:
1. V
DDA
and V
DDS
supplies must be hardwired together to the same power supply.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
5
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