FAN7389 — 3-Phase Half-Bridge Gate-Drive IC
September 2012
FAN7389
3-Phase Half-Bridge Gate-Drive IC
Features
Floating Channel for Bootstrap Operation to +600 V
Typically 350 mA/650 mA Sourcing/Sinking Current
Driving Capability for All Channels
Extended Allowable Negative V
S
Swing to -9.8 V for
Signal Propagation at V
DD
=V
BS
=15 V
Output In-Phase with Input Signal
Over-Current Shutdown Turns off All Six Drivers
Matched Propagation Delay for All Channels
3.3 V and 5.0 V Input Logic Compatible
Adjustable Fault-Clear Timing
Built-in Advanced Input Filter
Built-in Shoot-Through Prevention Logic
Built-in Soft Turn-Off Function
Common-Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for All Channels
Description
The FAN7389 is a monolithic three-phase half-bridge
gate-drive IC designed for high-voltage, high-speed
driving MOSFETs and IGBTs operating up to +600 V.
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to V
S
= -9.8 V (typical) for V
BS
=15 V.
The protection functions include under-voltage lockout
and inverter over-current trip with an automatic fault-
clear function.
Over-current protection that terminates all six outputs
can be derived from an external current-sense resistor.
An open-drain fault signal is provided to indicate that an
over-current or under-voltage shutdown has occurred.
The UVLO circuits prevent malfunction when V
DD
and
V
BS
are lower than the specified threshold voltage.
Output drivers typically source and sink 350 mA and
650 mA, respectively; which is suitable for three-phase
half-bridge applications in motor drive systems.
Applications
3-Phase Motor Inverter Driver
Air Conditioners
Washing Machines
General-Purpose Three-Phase Inverters
28-SOIC
Ordering Information
Part Number
FAN7389MX1
(1)
Package
28-Lead, Small Outline Integrated Circuit Wide Body (SOIC)
Operating
Temperature
-40 to +125°C
Packing
Method
Tape & Reel
Note:
1. These devices passed wave soldering test by JESD22A-111.
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.2
www.fairchildsemi.com
FAN7389 — 3-Phase Half-Bridge Gate-Drive IC
Typical Application Diagram
Figure 1. 3-Phase BLDC Motor Drive Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.2
www.fairchildsemi.com
2
FAN7389 — 3-Phase Half-Bridge Gate-Drive IC
Pin Configuration
Figure 3. Pin Configuration
Pin Definitions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17, 21, 25
18
19
20
22
23
24
26
27
28
Name
V
DD
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
FO
CS
EN
RCIN
V
SS
COM
LO3
LO2
LO1
NC
V
S3
HO3
V
B3
V
S2
HO2
V
B2
V
S1
HO1
V
B1
Description
Logic and low-side gate driver power supply voltage
Logic Input 1 for high-side gate 1 driver
Logic Input 2 for high-side gate 2 driver
Logic Input 3 for high-side gate 3 driver
Logic Input 1 for low-side gate 1 driver
Logic Input 2 for low-side gate 2 driver
Logic Input 3 for low-side gate 3 driver
Fault output with open drain (indicates over-current and low-side under-voltage)
Analog input for over-current shutdown
Logic input for shutdown functionality
An external RC network input used to define the fault-clear delay
Logic ground
Low-side driver return
Low-side gate driver 3 output
Low-side gate driver 2 output
Low-side gate driver 1 output
No connect
High-side driver 3 floating supply offset voltage
High-side driver 3 gate driver output
High-side driver 3 floating supply
High-side driver 2 floating supply offset voltage
High-side driver 2 gate driver output
High-side driver 2 floating supply
High-side driver 1 floating supply offset voltage
High-side driver 1 gate driver output
High-side driver 1 floating supply
www.fairchildsemi.com
3
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.2
FAN7389 — 3-Phase Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
A
=25°C, unless otherwise specified.
Symbol
V
S
V
B
V
DD
V
HO
V
LO
V
IN
V
FO
PW
HIN
dV
S
/dt
P
D
θ
JA
T
J
T
STG
Parameter
High-Side Floating Offset Voltage
High-Side Floating Supply Voltage
Low-Side and Logic-Fixed Supply Voltage
High-Side Floating Output Voltage V
HO1,2,3
Low-Side Floating Output Voltage V
LO1,2,3
Input Voltage (HINx, LINx, CS, and EN)
Fault Output Voltage ( FO )
High-Side Input Pulse Width
Allowable Offset Voltage Slew Rate
Power Dissipation
(2,3,4)
Thermal Resistance
Junction Temperature
Storage Temperature
Min.
V
B1,2,3
-25.0
-0.3
-0.3
V
S1,2,3
-0.3
-0.3
-0.3
-0.3
500
Max.
V
B1,2,3
+0.3
625.0
25.0
V
B1,2,3
+0.3
V
DD
+0.3
5.5
V
DD
+0.3
±50
1.4
70
150
Unit
V
V
V
V
V
V
V
ns
V/ns
W
°C/W
°C
°C
-55
150
Notes:
2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
4. Do not exceed P
D
under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
B1,2,3
V
S1,2,3
V
DD
V
HO1,2,3
V
LO1,2,3
V
FO
V
CS
V
IN
V
SS
T
A
Parameter
High-Side Floating Supply Voltage
High-Side Floating Supply Offset Voltage
Low-Side and Logic Fixed Supply Voltage
High-Side Output Voltage
Low-Side Output Voltage
Fault Output Voltage ( FO )
Current-Sense Pin Input Voltage
Logic Input Voltage (HIN1,2,3 and LIN1,2,3)
Logic Ground
Ambient Temperature
Min.
V
S1,2,3
+10
6-V
DD
10
V
S1,2,3
COM
COM
COM
COM
-5
-40
Max.
V
S1,2,3
+20
600
20
V
B1,2,3
V
DD
V
DD
5
5
5
+125
Unit
V
V
V
V
V
V
V
V
V
°C
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.2
www.fairchildsemi.com
4
FAN7389 — 3-Phase Half-Bridge Gate-Drive IC
Electrical Characteristics
V
BIAS
(V
DD
, V
BS1,2,3
) = 15.0 V and T
A
= 25°C unless otherwise specified. The V
IN
and I
IN
parameters are referenced to
COM and are applicable to all six channels. The V
O
and I
O
parameters are referenced to V
S1,2,3
and COM and are
applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V
DDUV
parameters are referenced to COM. The
V
BSUV
parameters are referenced to V
S1,2,3
.
Symbol
I
QDD
I
PDD
V
DDUV+
V
DDUV-
V
DDHYS
Parameter
Quiescent V
DD
Supply Current
Operating V
DD
Supply Current
V
DD
Supply Under-Voltage Positive-Going
Threshold
V
DD
Supply Under-Voltage Negative-Going
Threshold
V
DD
Supply Under-Voltage Lockout
Hysteresis
V
BS
Supply Under-Voltage Positive-Going
Threshold
V
BS
Supply Under-Voltage Negative-Going
Threshold
V
BS
Supply Under-Voltage Lockout
Hysteresis
Offset Supply Leakage Current
Quiescent V
BS
Supply Current
Operating V
BS
Supply Current
High-Level Output voltage, V
BIAS
-V
O
Low-Level Output voltage, V
O
Output HIGH Short-Circuit Pulse Current
(5)
Output LOW Short-Circuit Pulsed Current
(5)
Allowable Negative V
S
Pin Voltage for HIN
Signal Propagation to HO
Logic "1" Input Voltage HIN1,2,3, LIN1,2,3
Logic "0" Input Voltage HIN1,2,3, LIN1,2,3
Logic Input Bias Current (HO=LO=HIGH)
Logic Input Bias Current (HO=LO=LOW)
Logic Input Pull-Down Resistance
Enable Positive-Going Threshold Voltage
Enable Negative-Going Threshold Voltage
Logic Enable “1” Input Bias Current
Logic Enable “0” Input Bias Current
V
IN
=5 V
V
IN
=0 V
Conditions
V
LIN1,2,3
=0 V or 5 V, EN=0 V
f
LIN1,2,3
=20 kHz, rms Value
V
DD
=Sweep
V
DD
=Sweep
V
DD
=Sweep
Min. Typ. Max. Unit
200
400
7.5
7.0
8.5
8.0
0.5
9.3
8.7
μA
μA
V
V
V
Low-Side Power Supply Section
Bootstrapped Power Supply Section
V
BSUV+
V
BSUV-
V
BSHYS
I
LK
I
QBS
I
PBS
V
OH
V
OL
I
O+
I
O-
V
S
V
BS1,2,3
=Sweep
V
BS1,2,3
=Sweep
V
BS1,2,3
=Sweep
V
B1,2,3
=V
S1,2,3
=600 V
V
HIN1,2,3
=0V or 5 V, EN=0V
f
HIN1,2,3
=20 kHz, rms Value
I
O
=0 mA (No Load)
I
O
=0 mA (No Load)
V
O
=0 V, V
IN
=5 V with PW≤10 µs
V
O
=15 V, V
IN
=0 V with
PW≤10 µs
250
500
350
650
-9.8
-7.0
10
200
50
420
7.5
7.0
8.5
8.0
0.5
10
80
480
100
100
9.3
8.7
V
V
V
μA
μA
μA
mV
mV
mA
mA
V
Gate Driver Output Section
Logic Input Section
V
IH
V
IL
I
IN+
I
IN-
R
IN
V
EN+
V
EN-
I
EN+
I
EN-
2.5
0.8
100
2
50
2.5
0.8
V
EN
=5 V (Pull-Down=150KΩ)
V
EN
=0 V
33
2
V
V
μA
μA
KΩ
V
V
μA
μA
Enable Control Section (EN)
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN7389 • Rev. 1.0.2
www.fairchildsemi.com
5
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