Ceramic transient voltage suppressors
SMD multilayer transient voltage suppressors, low
capacitance series
Series/Type:
Date:
November 2012
© EPCOS AG 2012. Reproduction, publication and dissemination of this publication, enclosures hereto and the
information contained therein without EPCOS' prior express consent is prohibited.
Multilayer varistors (MLVs)
Low capacitance series
EPCOS type designation system for low capacitance series
CA
Construction:
CT Single chip
with nickel barrier
termination
(AgNiSn)
CA Chip array
with nickel barrier
termination
(AgNiSn)
Case sizes:
0603 0603 single chip
0805 0805 single chip
06 0612 array
Number of elements per component:
Single chip
P2 Array with 2 elements
P4 Array with 4 elements
Tolerance of the varistor voltage:
K
±10%
S Special tolerance
Maximum RMS operating voltage (V
RMS
):
17 17 V
Special features:
Standard
A Special tolerance
T Internal coding
Low capacitance series
Taping mode:
G 180-mm reel
04
P2
S
17
T
LC
G
Please read
Cautions and warnings
and
Important notes
at the end of this document.
Page 2 of 34
Multilayer varistors (MLVs)
Low capacitance series
Features
ESD protection level acc. ISO 10605, IEC 61000-4-2
Level 4
Bidirectional protection
Low capacitance
Low insertion loss
Low leakage current
No signal distortion
RoHS-compatible
Suitable for lead-free soldering
PSpice simulation models available
Customer-specific types on request
Applications
ESD protection of data lines e.g. in notebooks and
portable devices
Design
Multilayer technology
Lack of plastic or epoxy encapsulation for
flammability rating better than UL 94 V-0
Termination (see “Soldering directions”):
CT and CA types with nickel barrier terminations
(AgNiSn), recommended for lead-free soldering,
and compatible with tin/lead solder.
V/I characteristics and derating curves
V/I and derating curves are attached to the data sheet.
The curves are sorted by V
RMS
and then by case size,
which is included in the type designation.
Single chip
Internal circuit
Available case sizes:
EIA
0603
0805
Array
Internal circuit
Metric
1608
2012
4-fold array
Available case sizes:
EIA
0612
Metric
1632
Version
4-fold array
Please read
Cautions and warnings
and
Important notes
at the end of this document.
Page 3 of 34
Multilayer varistors (MLVs)
Low capacitance series
General technical data
Maximum RMS operating voltage
Maximum DC operating voltage
Contact discharge ESD capability
Air discharge ESD capability
Maximum surge current
Maximum capacitance
Maximum clamping voltage
Operating temperature
Storage temperature
V
RMS,max
V
DC,max
to IEC 61000-4-2
V
ESD,contact
to IEC 61000-4-2
V
ESD,air
(8/20 µs)
I
surge,max
(1 MHz, 1 V)
C
max
(8/20 µs)
V
clamp,max
for arrays
T
op
for case size
≥
0603 T
op
for arrays
LCT/UCT
for case size
≥
0603 LCT/UCT
17
22
8
15
10 ... 30
50 ... 100
50
40/+85
55/+125
40/+125
55/+150
V
V
kV
kV
A
pF
V
°C
°C
°C
°C
Temperature derating
Climatic category:
40/+85
°C
for arrays
Climatic category:
chip size
≥
0603
55/+125
°C
for
Please read
Cautions and warnings
and
Important notes
at the end of this document.
Page 4 of 34
Multilayer varistors (MLVs)
Low capacitance series
Electrical specifications and ordering codes
Maximum ratings (T
op,max
)
Type
Ordering code
V
RMS,max
V
DC,max
I
surge,max
W
max
P
diss,max
T
op,max
(8/20 µs) (2 ms)
V
V
A
mJ
mW
°C
22
22
22
22
30
10
30
30
75
100
75
100
3
1
3
4
+85
+125
+125
+125
4-fold array
CA06P4S17TLCG
Single chip
CT0603K17LCG
CT0603S17ALCG
CT0805K17LCG
B72724A2170S162 17
B72500T2170K060 17
B72500T2170S160 17
B72510T2170K062 17
Characteristics (T
A
= 25
°C)
Type
V
V,min
(1 mA)
V
25
24.3
25
24.8
V
V,max
(1 mA)
V
40
29.7
40
33
V
clamp,max
V
50
50
50
50
I
clamp
(8/20 µs)
A
1
1
1
1
C
max
(1 MHz, 1 V)
pF
75
50
75
100
4-fold array
CA06P4S17TLCG
Single chip
CT0603K17LCG
CT0603S17ALCG
CT0805K17LCG
Please read
Cautions and warnings
and
Important notes
at the end of this document.
Page 5 of 34
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
