February 2010
74LVX3245
8-Bit Dual Supply Translating Transceiver with
3-STATE Outputs
General Description
The LVX3245 is a dual-supply, 8-bit translating transceiver
that is designed to interface between a 3V bus and a 5V
bus in a mixed 3V/5V supply environment. The Transmit/
Receive (T/R) input determines the direction of data flow.
Transmit (active-HIGH) enables data from A Ports to B
Ports; Receive (active-LOW) enables data from B Ports to
A Ports. The Output Enable input, when HIGH, disables
both A and B Ports by placing them in a high impedance
condition. The A Port interfaces with the 3V bus; the B Port
interfaces with the 5V bus.
The LVX3245 is suitable for mixed voltage applications
such as notebook computers using 3.3V CPU and 5V
peripheral components.
Features
■
Bidirectional interface between 3V and 5V buses
■
Inputs compatible with TTL level
■
3V data flow at A Port and 5V data flow at B Port
■
Outputs source/sink 24 mA
■
Guaranteed simultaneous switching noise level and
dynamic threshold performance
■
Implements proprietary EMI reduction circuitry
■
Functionally compatible with the 74 series 245
Ordering Code:
Order Number
74LVX3245WM
74LVX3245QSC
74LVX3245MTC
Package Number
M24B
MQA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol/s
Connection Diagram/s
Pin Descriptions
Pin Names
OE
T/R
A
0
–A
7
B
0
–B
7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Truth Table/s
Inputs
OE
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Outputs
T/R
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
Logic Diagram/s
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2
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CCA
, V
CCB
)
DC Input Voltage (V
I
) @ OE, T/R
DC Input/Output Voltage (V
I/O
)
@ A
n
@ B
n
DC Input Diode Current (I
IN
)
@ OE, T/R
DC Output Diode Current (I
OK
)
DC Output Source or
Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
and Max Current @ I
CCA
@ I
CCB
Storage Temperature Range (T
STG
)
DC Latch-Up Source or
Sink Current
Maximum Junction Temperature
Under Bias (T
J
)
±300
mA
+150°C
±50
mA
±100
mA
±200
mA
−65°C
to
+150°C
±50
mA
±20
mA
±50
mA
−0.5V
to V
CCA
+
0.5V
−0.5V
to V
CCB
+
0.5V
−0.5V
to
+7.0V
−0.5V
to V
CCA
+
0.5V
Recommended Operating
Conditions
(Note 2)
Supply Voltage
V
CCA
V
CCB
Input Voltage (V
I
) @ OE, T/R
Input/Output Voltage (V
I/O
)
@ A
n
@ B
n
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (Δt/ΔV)
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused Pins (inputs and I/Os) must be held HIGH or LOW. They
may not float.
2.7V to 3.6V
4.5V to 5.5V
0V to V
CCA
0V to V
CCA
0V to V
CCB
−40°C
to
+85°C
8 ns/V
DC Electrical Characteristics
Symbol
V
IHA
V
IHB
V
ILA
V
ILB
V
OHA
Minimum HIGH Level
Output Voltage
Maximum LOW Level
Input Voltage
Parameter
Minimum HIGH Level
Input Voltage
A
n
, T/R,
OE
B
n
A
n
, T/R,
OE
B
n
V
CCA
(V)
3.6
2.7
3.3
3.3
3.6
2.7
3.3
3.3
3.0
3.0
2.7
2.7
V
OHB
V
OLA
Maximum LOW Level
Output Voltage
3.0
3.0
3.0
3.0
2.7
2.7
V
OLB
I
IN
Maximum Input
Leakage Current
@ OE, T/R
I
OZA
Maximum 3-STATE
Output Leakage
@ A
n
I
OZB
Maximum 3-STATE
Output Leakage
@ B
n
3.6
5.5
±0.5
±5.0
μA
3.6
5.5
±0.5
±5.0
μA
V
I
=
V
IL
, V
IH
OE
=
V
CCA
V
O
=
V
CCA
, GND
V
I
=
V
IL
, V
IH
OE
=
V
CCA
V
O
=
V
CCB
, GND
3.6
5.5
±0.1
±1.0
μA
V
I
=
V
CCB
, GND
3.0
3.0
V
CCB
(V)
5.0
5.0
4.5
5.5
5.0
5.0
4.5
5.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
2.99
2.65
2.5
2.3
4.5
4.25
0.002
0.21
0.11
0.22
0.002
0.18
T
A
= +25°C
Typ
2.0
2.0
2.0
2.0
0.8
0.8
0.8
0.8
2.9
2.35
2.3
2.1
4.4
3.86
0.1
0.36
0.36
0.42
0.1
0.36
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
2.0
2.0
0.8
0.8
0.8
0.8
2.9
2.25
2.2
2.0
4.4
3.76
0.1
0.44
0.44
0.5
0.1
0.44
V
V
V
V
I
OUT
= −100 μA
I
OH
= −24
mA
I
OH
= −12
mA
I
OH
= −24
mA
I
OUT
= −100 μA
I
OH
= −24
mA
I
OUT
=100 μA
I
OL
=
24 mA
I
OL
=
12 mA
I
OL
=
24 mA
I
OUT
=
100
μA
I
OL
=
24 mA
V
V
OUT
≤
0.1V or
≥
V
CC
−0.1V
V
V
OUT
≤
0.1V or
≥
V
CC
−
0.1V
Units
Conditions
3
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Symbol
ΔI
CC
Maximum
Parameter
B
n
A
n
, T/R,
OE
V
CCA
(V)
3.6
3.6
V
CCB
(V)
5.5
5.5
T
A
= +25°C
Typ
1.0
1.35
0.35
T
A
= −40°C
to
+85°C
Guaranteed Limits
1.5
0.5
Units
mA
mA
Conditions
V
I
=
V
CCB
−
2.1V
V
I
=
V
CCA
−0.6V
A
n
=
V
CCA
or GND
I
CCT
/Input @
I
CCA
Quiescent V
CCA
Supply Current
I
CCB
Quiescent V
CCB
Supply Current
V
OLPA
V
OLPB
V
OLVA
V
OLVB
V
IHDA
V
IHDB
V
ILDA
V
ILDB
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
3.6
5.5
5
50
μA
B
n
=
V
CCB
or GND,
OE
=
GND, T/R
=
GND
A
n
=
V
CCA
or GND
3.6
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5.5
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
8
0.8
1.5
−0.8
−1.2
2.0
2.0
0.8
0.8
80
μA
B
n
=
V
CCB
or GND,
OE
=
GND, T/R
=
V
CCA
(Note 3) (Note 4)
(Note 3) (Note 4)
(Note 3) (Note 5)
(Note 3) (Note 5)
V
V
V
V
Note 3:
Worst case package.
Note 4:
Max number of outputs defined as (n). Data inputs are driven 0V to V
CC
level; one output at GND.
Note 5:
Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to V
CC
level. Input-under-test switching:
V
CC
level to threshold (V
IHD
), 0V to threshold (V
ILD
), f
=
1 MHz.
AC Electrical Characteristics
T
A
= +25°C
C
L
=
50 pF
Symbol
Parameters
V
CCA
=
3.3V (Note 6)
V
CCB
=
5.0V (Note 7)
Min
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PZL
t
PZH
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Propagation Delay
A to B
Propagation Delay
B to A
Output Enable
Time OE to B
Output Enable
Time OE to A
Output Disable
Time OE to B
Output Disable
Time OE to A
Output to Output
Skew (Note 8)
Data to Output
Note 6:
Voltage Range 3.3V is 3.3V
±
0.3V.
Note 7:
Voltage Range 5.0V is 5.0V
±
0.5V.
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
T
A
= −40°C
to
+85°C
C
L
=
50 pF
V
CCA
=
3.3V (Note 6)
V
CCB
=
5.0V (Note 7)
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
8.5
8.0
8.0
8.0
8.5
9.0
9.0
9.5
8.0
7.5
8.5
7.0
1.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
V
CCA
=
2.7V
V
CCB
=
5.0V (Note 7)
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
9.0
8.5
8.5
8.5
9.0
9.5
9.5
10.0
8.5
8.0
9.0
7.5
1.5
ns
ns
ns
ns
ns
ns
Units
Typ
5.4
5.6
5.1
5.7
4.8
6.3
6.3
6.8
5.3
4.2
5.3
3.7
1.0
Max
8.0
7.5
7.5
7.5
8.0
8.5
8.5
9.0
7.5
7.0
8.0
6.5
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
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4
Capacitance
Symbol
C
IN
C
I/O
C
PD
Input Capacitance
Input/Output
Capacitance
Power Dissipation
Capacitance (Note 9)
Note 9:
C
PD
is measured at 10 MHz
Parameter
Typ
4.5
15
A
→
B
B
→
A
55
40
Units
pF
pF
pF
V
CC
=
Open
V
CCA
=
3.3V
V
CCB
=
5.0V
V
CCB
=
5.0V
V
CCA
=
3.3V
Conditions
8-Bit Dual Supply Translating Transceiver
The LVX3245 is a dual supply device capable of bidirec-
tional signal translation. This level shifting ability provides
an efficient interface between low voltage CPU local bus
with memory and a standard bus defined by 5V I/O levels.
The device control inputs can be controlled by either the
low voltage CPU and core logic or a bus arbitrator with 5V
I/O levels.
Manufactured on a sub-micron CMOS process, the
LVX3245 is ideal for mixed voltage applications such as
notebook computers using 3.3V CPU's and 5V peripheral
devices.
Power Up Considerations
To insure that the system does not experience unneces-
sary I
CC
current draw, bus contention, or oscillations during
power up, the following guidelines should be adhered to
(refer to Table 1):
• Power up the control side of the device first. This is the
V
CCA
.
• OE should ramp with or ahead of V
CCA
. This will help
guard against bus contention.
• The Transmit/Receive control pin (T/R) should ramp with
V
CCA
, this will ensure that the A Port data pins are con-
figured as inputs. With V
CCA
receiving power first, the A
I/O Port should be configured as inputs to help guard
against bus contention and oscillations.
• A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Device Type
74LVX3245
V
CCA
3V
(power up 1st)
V
CCB
5V
configurable
T/R
ramp
with V
CCA
OE
ramp
with V
CCA
A Side I/O
logic
0V or V
CCA
B Side I/O
outputs
Floatable Pin
Allowed
No
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
5
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