SB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The SB3N551 is a low skew 1−to−4 clock fanout buffer, designed
for clock distribution in mind. The SB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin three−states the outputs when low.
Features
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MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
3N551
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
3N551
ALYW
G
•
•
•
•
•
•
•
•
•
Input/Output Clock Frequency up to 160 MHz
Low Skew Outputs (50 ps typical)
RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
Output goes to Three−State Mode via OE
Operating Range: V
DD
= 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
PIN CONNECTIONS
I
CLK
Q1
1
2
3
4
8
7
6
5
OE
V
DD
GND
Q4
Q1
Q2
CLK
Q3
Q4
Q2
Q3
ORDERING INFORMATION
Device
SB3N551DG
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Shipping
†
98 Units/Rail
2500/Tape & Reel
OE
SB3N551DR2G
Figure 1. Block Diagram
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
January, 2015 − Rev. 0
Publication Order Number:
SB3N551/D
SB3N551
Table 1. OE, OUTPUT ENABLE FUNCTION
OE
0
1
Function
Disable
Enable
Table 2. PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
−
Name
I
CLK
Q1
Q2
Q3
Q4
GND
V
DD
OE
EP
Type
(LV)CMOS/(LV)TTL Input
(LV)CMOS/(LV)TTL Output
(LV)CMOS/(LV)TTL Output
(LV)CMOS/(LV)TTL Output
(LV)CMOS/(LV)TTL Output
Power
Power
(LV)CMOS/(LV)TTL Input
Thermal Exposed Pad
Description
Clock Input. Internal pull-up resistor.
Clock Output 1
Clock Output 2
Clock Output 3
Clock Output 4
Negative supply voltage; Connect to ground, 0 V
Positive supply voltage (3.0 V to 5.5 V)
Output Enable for the clock outputs. Outputs are enabled when HIGH or when left
open; OE pin has internal pull−up resistor. Three−states outputs when LOW.
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave uncon-
nected, floating open.
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2
SB3N551
Table 3. MAXIMUM RATINGS
Symbol
V
DD
V
I
/V
O
T
A
T
stg
q
JA
q
JC
Parameter
Positive Power Supply
Input/Output Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Condition 1
GND = 0 V
t
≤
1.5 ns
−
−
0 lfpm
500 lfpm
(Note 1)
Condition 2
−
−
−
−
SOIC−8
SOIC−8
Rating
7.0
GND–1.5
≤
V
I
/V
O
≤
V
DD
+1.5
≥
−40 to
≤
+85
−65 to +150
190
130
41 to 44
Units
V
V
°C
°C
°C/W
°C/W
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Value
> 4 kV
> 200 V
Level 1
UL−94 code V−0 @ 0.125 in
531 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Transistor Count
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Oxygen Index: 28 to 34
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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SB3N551
Table 5. DC CHARACTERISTICS
(V
DD
= 3.0 V to 3.6 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
I
DD
V
OH
V
OL
V
OH
V
IH,
I
CLK
V
IL,
I
CLK
V
IH,
OE
V
IL,
OE
ZO
RPU
CIN
IOS
Characteristic
Power Supply Current @ 135 MHz, No Load, V
DD
= 3.3 V
Output HIGH Voltage – I
OH
= −25 mA, V
DD
= 3.3 V
Output LOW Voltage – I
OL
= 25 mA
Output HIGH Voltage – I
OH
= −12 mA (CMOS level)
Input HIGH Voltage, I
CLK
Input LOW Voltage, I
CLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Pull−up Resistor, OE
Input Capacitance, OE
Short Circuit Current
Min
−
2.4
−
V
DD
− 0.4
(V
DD
/2)+0.7
−
2.0
0
−
−
−
−
Typ
20
−
−
−
−
−
−
−
20
220
5.0
±
50
Max
40
−
0.4
−
3.8
(V
DD
/2)−0.7
VDD
0.8
−
−
−
−
Unit
mA
V
V
V
V
V
V
V
W
kW
pF
mA
DC CHARACTERISTICS
(V
DD
= 4.5 V to 5.5 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
I
DD
V
OH
V
OL
V
OH
V
IH,
I
CLK
V
IL,
I
CLK
V
IH,
OE
V
IL,
OE
ZO
RPU
CIN
IOS
Characteristic
Power Supply Current @ 135 MHz, No Load, V
DD
= 5.0 V
Output HIGH Voltage – I
OH
= −35 mA
Output LOW Voltage – I
OL
= 35 mA
Output HIGH Voltage – I
OH
= −12 mA (CMOS level)
Input HIGH Voltage, I
CLK
Input LOW Voltage, I
CLK
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Pull−up Resistor, OE
Input Capacitance, OE
Short Circuit Current
Min
−
2.4
−
V
DD
– 0.4
(V
DD
/2) + 1
−
2.0
0
−
−
−
−
Typ
50
−
−
−
−
−
−
−
20
220
5.0
±80
Max
95
−
0.4
−
5.5
(V
DD
/2) − 1
V
DD
0.8
−
−
−
−
Unit
mA
V
V
V
V
V
V
V
W
kW
pF
mA
Table 6. AC CHARACTERISTICS
(V
DD
= 3.0 V to 5.5 V, GND = 0 V, T
A
= −40°C to +85°C) (Note 3)
Symbol
f
in
t
jitter
(f)
t
jitter (pd)
t
r
/t
f
t
pd
t
skew
Input Frequency
RMS Phase Jitter (Integrated 12 kHz − 20 MHz)
(See Figures 2 and 3)
Period Jitter (RMS, 1s)
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Qn, 0 − 180 MHz,
(Note 4)
Output−to−Output Skew; (Note 5)
f
carrier
= 25 MHz
f
carrier
= 50 MHz
Characteristic
Conditions
Min
−
−
−
−
−
1.5
−
Typ
−
43
16
2.0
0.5
3.0
50
Max
160
−
−
−
1.0
6.0
250
Unit
MHz
fs
ps
ns
ns
ps
3. Outputs loaded with external R
L
= 33−W series resistor and C
L
= 15 pF to GND. Duty cycle out = duty in. A 0.01
mF
decoupling capacitor
should be connected between V
DD
and GND. A 33
W
series terminating resistor may be used on each clock output if the trace is longer than
1 inch.
4. Measured with rail−to−rail input clock.
5. Measured on rising edges at V
DD
÷
2.
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SB3N551
Figure 2. Phase Noise Plot at 25 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above plot captured using Agilent E5052A shows Additive Phase Noise of the SB3N551 device measured with an input
source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;
as shown in the shaded region of the plot) is 43 fs (RMS Jitter of the input source is 203.31 fs and Output (DUT+Source) is
247.06 fs).
Figure 3. Phase Noise Plot at 50 MHz at an Operating Voltage of 5 V, Room Temperature
The above plot captured using Agilent E5052A shows Additive Phase Noise of the SB3N551 device measured with an input
source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;
as shown in the shaded region of the plot) is 16 fs (RMS Jitter of the input source is 104.08 fs and Output (DUT + Source) is
119.77 fs).
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