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MT48LC4M32B2P: 产品描述SDR SDRAM MT48LC4M32B2 â 1 Meg x 32 x 4 Banks; 文件大小4MB，共79页; 制造商Micron(美光); 官网地址http://www.micron.com/

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MT48LC4M32B2P概述

SDR SDRAM MT48LC4M32B2 â 1 Meg x 32 x 4 Banks

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128Mb: x32 SDRAM

Features

SDR SDRAM

MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

Features

• PC100-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 4096-cycle refresh (commercial and

industrial)

– 16ms, 4096-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

Options

• Configuration

– 4 Meg x 32 (1 Meg x 32 x 4 banks)

• Package – OCPL

– 86-pin TSOP II (400 mil)

– 86-pin TSOP II (400 mil) Pb-free

– 90-ball VFBGA (8mm x 13mm)

– 90-ball VFBGA (8mm x 13mm) Pb-

free

• Timing (cycle time)

– 6ns (166 MHz)

– 7ns (143 MHz)

• Revision

• Operating temperature range

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

– Automotive (–40°C to +105°C)

Notes:

Off-center parting line.

Available only on Revision L.

Available only on Revision G.

Contact Micron for availability.

Marking

4M32B2

-6A

-6

-7

:G/:L

None

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-6A

-6

-7

Clock

Frequency (MHz)

167

143

Target

RCD-

RP-CL

3-3-3

RCD

(ns)

CL (ns)

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x32 SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagram ................................................................................................................................ 8

Pin and Ball Assignments and Descriptions ....................................................................................................... 9

Package Dimensions ....................................................................................................................................... 12

Temperature and Thermal Impedance ............................................................................................................ 14

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – I

Parameters ........................................................................................................ 18

Electrical Specifications – AC Operating Conditions ......................................................................................... 20

Functional Description ................................................................................................................................... 23

Commands .................................................................................................................................................... 24

COMMAND INHIBIT .................................................................................................................................. 24

NO OPERATION (NOP) ............................................................................................................................... 25

LOAD MODE REGISTER (LMR) ................................................................................................................... 25

ACTIVE ...................................................................................................................................................... 25

READ ......................................................................................................................................................... 26

WRITE ....................................................................................................................................................... 27

PRECHARGE .............................................................................................................................................. 28

BURST TERMINATE ................................................................................................................................... 28

REFRESH ................................................................................................................................................... 29

AUTO REFRESH ..................................................................................................................................... 29

SELF REFRESH ....................................................................................................................................... 29

Truth Tables ................................................................................................................................................... 30

Initialization .................................................................................................................................................. 35

Mode Register ................................................................................................................................................ 37

Burst Length .............................................................................................................................................. 39

Burst Type .................................................................................................................................................. 39

CAS Latency ............................................................................................................................................... 41

Operating Mode ......................................................................................................................................... 41

Write Burst Mode ....................................................................................................................................... 41

Bank/Row Activation ...................................................................................................................................... 42

READ Operation ............................................................................................................................................. 43

WRITE Operation ........................................................................................................................................... 52

Burst Read/Single Write .............................................................................................................................. 59

PRECHARGE Operation .................................................................................................................................. 60

Auto Precharge ........................................................................................................................................... 60

AUTO REFRESH Operation ............................................................................................................................. 72

SELF REFRESH Operation ............................................................................................................................... 74

Power-Down .................................................................................................................................................. 76

Clock Suspend ............................................................................................................................................... 77

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x32 SDRAM

Features

List of Figures

Figure 1: 4 Meg x 32 Functional Block Diagram ................................................................................................. 8

Figure 2: 86-Pin TSOP Pin Assignments (Top View) ........................................................................................... 9

Figure 3: 90-Ball FBGA Ball Assignments (Top View) ....................................................................................... 10

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12

Figure 5: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 13

Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 15

Figure 7: Example: Temperature Test Point Location, 90-Ball VFBGA (Top View) .............................................. 16

Figure 8: ACTIVE Command .......................................................................................................................... 25

Figure 9: READ Command ............................................................................................................................. 26

Figure 10: WRITE Command ......................................................................................................................... 27

Figure 11: PRECHARGE Command ................................................................................................................ 28

Figure 12: Initialize and Load Mode Register .................................................................................................. 36

Figure 13: Mode Register Definition ............................................................................................................... 38

Figure 14: CAS Latency .................................................................................................................................. 41

Figure 15: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 42

Figure 16: Consecutive READ Bursts .............................................................................................................. 44

Figure 17: Random READ Accesses ................................................................................................................ 45

Figure 18: READ-to-WRITE ............................................................................................................................ 46

Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 47

Figure 20: READ-to-PRECHARGE .................................................................................................................. 47

Figure 21: Terminating a READ Burst ............................................................................................................. 48

Figure 22: Alternating Bank Read Accesses ..................................................................................................... 49

Figure 23: READ Continuous Page Burst ......................................................................................................... 50

Figure 24: READ – DQM Operation ................................................................................................................ 51

Figure 25: WRITE Burst ................................................................................................................................. 52

Figure 26: WRITE-to-WRITE .......................................................................................................................... 53

Figure 27: Random WRITE Cycles .................................................................................................................. 54

Figure 28: WRITE-to-READ ............................................................................................................................ 54

Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 55

Figure 30: Terminating a WRITE Burst ............................................................................................................ 56

Figure 31: Alternating Bank Write Accesses ..................................................................................................... 57

Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 58

Figure 33: WRITE – DQM Operation ............................................................................................................... 59

Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 61

Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 62

Figure 36: READ With Auto Precharge ............................................................................................................ 63

Figure 37: READ Without Auto Precharge ....................................................................................................... 64

Figure 38: Single READ With Auto Precharge .................................................................................................. 65

Figure 39: Single READ Without Auto Precharge ............................................................................................. 66

Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 67

Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 67

Figure 42: WRITE With Auto Precharge ........................................................................................................... 68

Figure 43: WRITE Without Auto Precharge ..................................................................................................... 69

Figure 44: Single WRITE With Auto Precharge ................................................................................................. 70

Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 71

Figure 46: Auto Refresh Mode ........................................................................................................................ 73

Figure 47: Self Refresh Mode .......................................................................................................................... 75

Figure 48: Power-Down Mode ........................................................................................................................ 76

Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 77

Figure 50: Clock Suspend During READ Burst ................................................................................................. 78

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MT48LC4M32B2P概述

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