SPT9691
WIDE INPUT VOLTAGE, JFET COMPARATOR
FEATURES
•
•
•
•
•
•
Common Mode Range -4.0 to +8.0 V
Low Input Bias Current <100 pA
Propagation Delay 2.5 ns (max)
Low Offset
±25
mV
Low Feedthrough and Crosstalk
Differential Latch Control
APPLICATIONS
•
•
•
•
•
•
•
•
Automated Test Equipment
High-Speed Instrumentation
Window Comparators
High-Speed Timing
Line Receivers
High-Speed Triggers
Threshold Detection
Peak Detection
GENERAL DESCRIPTION
The SPT9691 is a high-speed, wide common mode voltage,
JFET input, dual comparator. It is designed for applications
that measure critical timing parameters in which wide com-
mon mode input voltages of -4.0 to +8.0 V are required.
Propagation delays are constant for overdrives greater than
200 mV.
JFET inputs reduce the input bias currents to the nanoamp
level, eliminating the need for input drivers and buffers in
most applications. The device has differential analog inputs
and complementary logic outputs compatible with ECL sys-
tems. Each comparator has a complementary latch enable
control that can be driven by standard ECL logic.
The SPT9691 is available in 20-lead PLCC, 20-lead plastic
DIP and 20-contact LCC packages over the commercial
temperature range. It is also available in die form.
BLOCK DIAGRAM
Q
A
Q
A
GND
A
LE
A
LE
A
DV
EE
(A)
AV
EE
(A)
AV
CC
(A)
-IN
A
+IN
A
A
B
Q
B
Q
B
GND
B
LE
B
LE
B
DV
EE
(B)
AV
EE
(B)
AV
CC
(B)
-IN
B
+IN
B
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages (Measured to GND)
Positive Supply Voltage (AV
CC
) .............. -0.5 to +11.0 V
Negative Supply Voltage (AV
EE
) ............ -11.0 to +0.5 V
Negative Supply Voltage (DV
EE
) .............. -6.0 to +0.5 V
Input Voltages
Input Common Mode Voltage ........ DV
EE
-1 to +AV
CC
+1
Differential Input Voltage ...................... -12.0 to +12.0 V
Input Voltage, Latch Controls .................. DV
EE
to 0.5 V
V
IN
to AV
CC
Differential Voltage ................ -16 to +1.0 V
V
IN
to AV
EE
Differential Voltage ................ +4 to +21.0 V
Note:
Output
Output Current ....................................................... 30 mA
Temperature
Operating Temperature, ambient .................. 0 to +70
°C
junction ....................... +150
°C
Lead Temperature, (soldering 60 seconds) ........ +300
°C
Storage Temperature ................................ -65 to +150
°C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications. Application of multiple maximum rating conditions at the same time may damage
the device.
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
AV
CC
= +10 V, AV
EE
=-10.0 V, DV
EE
=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.
PARAMETERS
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage
Offset Voltage Tempco
Input Bias Current
Input Bias Current
Input Offset Current
Input Offset Current
Positive Supply Current (Dual)
Negative Supply Current (Dual)
Negative Supply Current (Dual)
Positive Supply Voltage, AV
CC
Negative Supply Voltage, AV
EE
Negative Supply Voltage, DV
EE
Input Common Mode Range
Latch Enable
Common Mode Range
Differential Voltage Range
Open Loop Gain
Differential Input Resistance
Input Capacitance
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX
UNITS
V
IN,CM
=0
T
MIN
< T
A
<T
MAX
I
IV
V
I
-25
-25
0.0
0.0
50
±0.1
±2.0
±1.0
±10
25
15
55
+25
+25
±10
±100
mV
mV
µV/°C
nA
nA
nA
nA
mA
mA
mA
V
V
V
V
V
V
dB
GΩ
pF
pF
pF
dB
dB
dB
T
MIN
<T
A
<T
MAX
T
MIN
<T
A
<T
MAX
AVcc=10 V
AV
EE
=-10.0 V
DV
EE
=-5.2 V
IV
V
V
I
I
I
IV
IV
IV
I
IV
I
V
V
9.75
-9.75
-4.95
-4.0
-2.0
33
20
70
10.25
-10.25
-5.45
+8.0
0
±10
10.0
-10.0
-5.2
60
2
1.0
1.0
2.9
LCC Package
PLCC Package
PDIP
Power Supply Sensitivity
Common Mode Rejection Ratio
T
MIN
< T
A
<T
MAX
V
I
IV
50
45
60
60
55
SPT
SPT9691
2
10/6/97
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
AV
CC
= +10 V, AV
EE
=-10.0 V, DV
EE
=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.
PARAMETERS
DC ELECTRICAL CHARACTERISTICS
Power Dissipation
Output High Level
Output Low Level
AC ELECTRICAL CHARACTERISTICS
Propagation Delay
1
Propagation Delay TEMPCO
Propagation Delay Skew (A vs B)
Propagation Delay Dispersion
2
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
Fall Time
Slew Rate
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX
UNITS
Dual
ECL 50 Ohms to -2V
ECL 50 Ohms to -2V
I
I
I
-.98
-1.95
700
895
-.70
-1.65
mW
V
V
150 mV O.D.
IV
V
V
1.5
2.0
2
100
200
1.7
0.8
2
-1.9
0.4
0.4
3
2.5
ns
ps/
°C
ps
ps
ns
ns
ns
ns
ns
ns
V/ns
150 mV Overdrive Min.
V
V
150 mV O.D.
V
V
V
20% to 80%
20% to 80%
V
V
V
NOTES:
1
Valid for both high-to-low and low-to-high transitions.
2
Dispersion is the change in propagation delay due to changes in slew rate, overdrive, and common mode level.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
SPT
SPT9691
3
10/6/97
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
If LE is high and LE low in the SPT9691, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
pdH
(Q or Q ). The input signal must be
maintained for a time t
s
(set-up time) before the LE falling
edge and
LE
rising edge and held for time t
H
after the falling
edge for the comparator to accept data. After t
H
, the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t
pL
is needed for strobe opera-
tion, and the output transitions occur after a time of t
pLOH
or
t
pLOL
.
Figure 1 - Timing Diagram
Latch Enable
50%
Latch Enable
t
H
t
S
Differential
Input Voltage
V
OD
Output Q
t
pdL
t
pLOH
50%
VRef ± VOS
tpL
50%
Output Q
t
pdH
V
IN
+=300 mV, V
OD
=150 mV
t
pLOL
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t
s
will be detected
and held; those occurring after t
H
will not be detected. Changes between t
S
and t
H
may not be detected.
SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output LOW to HIGH transition.
t
pdL
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
t
H
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
t
pL
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
t
S
V
OD
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
SPT
SPT9691
4
10/6/97
TYPICAL PERFORMANCE CURVES
INPUT OFFSET VOLTAGE VS COMMON MODE VOLTAGE
(T=+25 °C)
+10.0
100
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
(+25 °C)
+6.0
10
INPUT OFFSET VOLTAGE (mV)
+2.0
INPUT BIAS CURRENT (nA)
-4.0
-1.6
+0.8
+3.2
+5.6
+8.0
1.0
-2.0
0.1
-6.0
0.01
-10.0
0.001
-4.0
-1.6
+0.8
+3.2
+5.6
+8.0
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
PROPOGATION DELAY TIME VS TEMPERATURE
(V
OD
=150 mV)
2.4
3.0
PROPAGATION DELAY TIME VS OVERDRIVE (mV)
PROPAGATION DELAY TIME (ns)
2.8
2.2
PROPAGATION DELAY TIME (ns)
2.6
2.0
2.4
2.2
1.8
2.0
1.6
1.8
1.4
0
50
100
150
200
250
300
350
0
+25
+50
+75
+100
TEMPERATURE (°C)
OVERDRIVE (mV)
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
-.90
HYSTERESIS VS
∆LATCH
20
-1.10
15
OUTPUT RISE AND FALL (V)
-1.30
HYSTERESIS (mV)
V
IN
(CM) = 0.0 V
10
-1.50
5
-1.70
-1.90
1.1
1.5
1.9
2.3
2.7
3.5
0
-20
0
20
40
60
TIME (ns)
∆LATCH
= (V
LE
- V
LE
) mV
SPT
SPT9691
5
10/6/97
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