SL2610
Wide Dynamic Range Image Reject MOPLL
Data Sheet
Features
•
•
•
•
•
•
•
•
•
Single chip mixer/oscillator PLL combination for
multi band tuner for DTT applications
Each mixer oscillator band optimized for wide
dynamic range
RF input stages allow for either single-ended or
differential drive
PLL frequency synthesizer designed for low
phase noise performance
Broadband output level detect with onset adjust
PLL frequency synthesizer compatible with
standard digital terrestrial offsets
Four integrated switching ports
I
2
C fast mode compliant
ESD protection (Normal ESD handling
procedures should be observed)
SL2610/IG/LH1Q
SL2610/IG/LH1N
SL2610/IG/LH2Q
SL2610/IG/LH2N
October 2004
Ordering Information
40
40
40
40
Pin
Pin
Pin
Pin
MLP
MLP
MLP
MLP
Tape & Reel, Bake & Drypack
Trays, Bake & Drypack
Tape & Reel, Bake & Drypack*
Trays, Bake & Drypack*
*Leadfree
-40°C to +85°C
Description
The SL2610 is a mixer oscillator intended primarily
for application in all band tuners, where it performs
image reject downconversion of the RF channel to a
standard 36 MHz or 44 MHz IF.
Each band consists of a low noise preamplifier/mixer
and local oscillator with an external varactor tuned
tank. The band outputs share a common low
impedance SAWF driver stage.
Frequency selection is controlled by the on-board I
2
C
bus frequency synthesizer. This block also controls
four general purpose switching ports for selecting the
prefilter/AGC stages.
Applications
•
•
•
•
Terrestrial digital receiver systems
Terrestrial analogue receiver systems
Cable receiver systems
Data communications systems
LO
HI
MID
BAND BAND BAND
CHARGE
PUMP
DRIVE
PROG
DIVIDER
~
~
~
IF
SELECT
XTAL
XTALCAP
~
REF
DIVIDER
CONVOP
CONVOPB
IFIP
IFIPB
IFOP
IFOPB
AGC BIAS
AGC OUT
PORT P0
PORT P1
PORT P2
PORT P3
Port
Interface
I
2
C
Interface
SDA SCL ADD
HI
LO
MID
BAND BAND BAND
Figure 1 - SL2610 Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
SL2610
Data Sheet
The SL2610 has high intermodulation intercept performance so offering high signal to spurious performance in
the presence of higher amplitude interferers or in the presence of a wide bandwidth composite input signal.
An output broadband level detect circuit is included for control of the tuner front end AGC.
LOLOWOPB
LOMIDOPB
LOLOWOP
LOMIDOP
LOHIOPB
LOHIIPB
LOHIOP
LOHIIP
VccLO
PORT P3
VccRF
HI INPUT
HI INPUTB
PORT P2
PORT P1
MID INPUT
MID INPUTB
VccRF
LO INPUT
Pin 1
VccLO
IFOPB
IFOP
AGCBIAS
VCCIF
IFIPB
IFIP
ADD
CONVOP
CONVOPB
VccDIG
LO INPUTB
PORT P0
AGCOUT
CHARGE PUMP
XTAL CAP
VccRF
DRIVE
XTAL
SDA
SCL
VEE
(PACKAGE
PADDLE)
LH40
Figure 2 - Pin Allocation Diagram
Quick Reference Data
Characteristics
Frequency range:
LOW band
MID band
HIGH band
Conversion gain *
Noise figure
Typical Image Reject
P1dB input referred, Converter section only
IP3 input referred, Converter section only
IP2 input referred, Converter section only
LO phase noise (free running)
@ 10 kHz offset
@ 100 kHz offset
PLL phase noise
Maximum composite output amplitude
* Assuming 2 dB shaping filter loss in external IF path.
50-500
50-500
200-900
32
±
2
13
35
106
14
48
-90
-110
-158
3
Units
MHz
MHz
MHz
dB
dB
dB
dBuV
dBm
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBm
2
Zarlink Semiconductor Inc.
R5
1K
8n2H
L6
VT
1K
BB555
5pF
36nH
R2
1K
R3
L3
C28
1
100nF
+30V
100pF
C16
D3
C15
+30V
C9
D2
4K7
R6
L5
R19
3
gnd
+5V
gnd
+5V
2
GND
10R
22nH
POWER
100pF
L1
D1
BB640
4K7
82nH
+5V
7pF
2p2
470uF
2p2
2p2
2p2
100pF
BB640
gnd
C1
R4
L4
C10
C36
C11
C12 C13
C14
CN2
120nH
C2
1u5H
37
40
38
39
35
34
36
33
32
31
L2
gnd
10nF
gnd
10R
10R
10nF
C30
gnd
R17
R18
C32
6p8F
20R
gnd
VccLO
VccLO
gnd
4K7
P3
1
PORT P3
+5V
IF O/P
29
Vcc RF
IF O/P B
30
gnd
2
R16
LOHIO/P
LOHII/PB
LOMIDOP
LOLOWOP
C29
C3
gnd
+5V
4
HIGH IP B
gnd
3
HIGH IP
Vcc IF
27
AGC BIAS
28
LOLOWOPB
LOMIDOPB
LOHIO/PB
+5V
LOHII/P
R1
10nF
C22
T1
IF OUT
SK4
IF OUT
10nF
C23
10nF
5:1
TP2
TP
RF IN (HIGH)
C4
1nF
IC1
C24
IF INPUT B
82pF
Vee = Pin 0 = PACKAGE PADDLE
26
1nF
SL2610
PORT P2
gnd
1nF
SK1
VR1
10K
HI IN
AGC
C33
gnd
10nF
gnd
P2
5
C26
L7
220nH
gnd
SL2610
LO INPUT B
Vcc RF
AGC OUT
PORT P0
DRIVE
CHARGE PUMP
XTAL CAP
XTAL
SDA
SCL
Gnd
C8
11
12
13
14
15
16
17
18
19
gnd
1nF
+5V
20
gnd
0
gnd
gnd
+5V
gnd
+5V
P0
C34
R20
10nF
10K
C19
C18
C17
47pF
100nF
47pF
R12
gnd
+30V
D4
R10
4K7
R11
4K7
P0
Figure 3 - SL2610 Evaluation Board Schematic
C25
IF INPUT
ADD
CONV OP
CONV OP B
Vcc DIG
23
22
2
24
25
1nF
+5V
750R
CN1
X1
gnd
4 MHz
P0
R13
TP
D5
R7
VT
20K
TP1
33K
3
Zarlink Semiconductor Inc.
P1
PORT P1
MID INPUT
MID IP B
Vcc RF
LO INPUT
6
7
C35
gnd
9
1nF
10nF
1
3
C5
C6
1nF
8
SK2
RF IN (MID)
MID IN
L8
C27
82pF
220nH
+5V
gnd
C7
10
1nF
CN3
+5V
21
ADDRESS
ADDRESS
RF IN (LOW)
SK3
gnd
LOW IN
C31
10nF
I2C Control
C20
47pF
gnd
I2C
P1
3
4
5
6
SDA
VDD
GND
SCL
750R
P1
R8
R9
18K
R14
C21
1n5F
D6
P2
750R
P2
R15
gnd
gnd
D7
P3
TR1
BCW31
750R
Data Sheet
P3
SL2610
Data Sheet
Figure 4 - SL2610 Evaluation Board Layout (Top)
Figure 5 - SL2610 Evaluation Board Layout (Bottom)
4
Zarlink Semiconductor Inc.
SL2610
1.0
Functional Description
Data Sheet
The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is intended
primarily for application in all band terrestrial tuners and requires a minimum external component count. It contains
all elements required for RF downconversion to a standard IF with the exception of external VCO tank circuits.
The pin allocation is contained in Figure 2 and the block diagram in Figure 1.
1.1
Mixer/oscillator section
In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner
prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or
single-ended, and achieves the specified minimum performance in both configurations. Band input impedances
and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are contained
in Figure 13 and Figure 14.
The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted to
the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local
oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9 and
10.
The output of the mixer is then fed to the converter output driver which presents a matched 200
Ω
differential load
to an external IF shaping filter.
The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a 50
Ω
output impedance to interface direct with the tuner SAW filter.
The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The
target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of the
target level is given in Figure 18.
1.2
PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated
with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers.
The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain and
reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully
programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is
4-bits and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1.
The output of the phase detector feeds a charge pump and loop amplifier section which when used with an external
loop filter integrates the current pulses into the varactor line voltage.
The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched to
port P0 by programming the device into test mode. The test modes are described in Table 5.
5
Zarlink Semiconductor Inc.
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