SX1231_10,SX1231_10 pdf中文资料,SX1231_10引脚图,SX1231

Datasheet> 器件分类 > SX1231_10

文档预览

SX1231_10: 产品描述Transceiver Low Power Integrated UHF Transceiver; 文件大小897KB，共81页; 制造商SEMTECH; 官网地址http://www.semtech.com

下载文档全文预览

SX1231_10概述

Transceiver Low Power Integrated UHF Transceiver

文档预览

下载PDF文档

全文
预览

SX1231

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

SX1231 Transceiver

Low Power Integrated UHF Transceiver

VBAT1&2

VR_ANA

VR_DIG

Oscillator

Σ/Δ

Modulators

Demodulator &

Bit Synchronizer

Decimation and

& Filtering

RESET

Power Distribution System

LNA

Single to

Differential

Mixers

RFIO

Control Registers - Shift Registers - SPI Interface

Packet Engine & 66 Bytes FIFO

SPI

RSSI

GND

Division by

2, 4 or 6

AFC

RXTX

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

PA0

Ramp &

Control

Tank

Inductor

Interpolation

& Filtering

VR_PA

Loop

Filter

Frac-N PLL

Synthesizer

PA_BOOST

PA1&2

32 MHz

XTAL

GND

GENERAL DESCRIPTION

The SX1231 is a highly integrated RF transceiver capable of

operation over a wide frequency range, including the 433,

868 and 915 MHz license-free ISM (Industry Scientific and

Medical) frequency bands. Its highly integrated architecture

allows for a minimum of external components whilst

maintaining maximum design flexibility. All major RF

communication parameters are programmable and most of

them can be dynamically set. The SX1231 offers the unique

advantage of programmable narrow-band and wide-band

communication modes without the need to modify external

components. The SX1231 is optimized for low power

consumption while offering high RF output power and

channelized operation. TrueRF™ technology enables a low-

cost external component count (elimination of the SAW

filter) whilst still satisfying ETSI and FCC regulations.

KEY PRODUCT FEATURES

High Sensitivity: down to -120 dBm at 1.2 kbps

High Selectivity: 16-tap FIR Channel Filter

Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,

80 dB Blocking Immunity, no Image Frequency response

Low current: Rx = 16 mA, 100nA register retention

Programmable Pout: -18 to +17 dBm in 1dB steps

Constant RF performance over voltage range of chip

FSK Bit rates up to 300 kb/s

Fully integrated synthesizer with a resolution of 61 Hz

FSK, GFSK, MSK, GMSK and OOK modulations

Built-in Bit Synchronizer performing Clock Recovery

Incoming Sync Word Recognition

115 dB+ Dynamic Range RSSI

Automatic RF Sense with ultra-fast AFC

Packet engine with CRC, AES-128 encryption and 66-

byte FIFO

Built-in temperature sensor and Low Battery indicator

APPLICATIONS

Automated Meter Reading

Wireless Sensor Networks

Home and Building Automation

Wireless Alarm and Security Systems

Industrial Monitoring and Control

ORDERING INFORMATION

Part Number

SX1231IMLTRT

Delivery

Tape & Reel

MOQ / Multiple

3000 pieces

MARKETS

Europe: EN 300-220-1

North America: FCC Part 15.247, 15.249, 15.231

Narrow Korean and Japanese bands

QFN 24 Package - Operating Range [-40;+85°C]

Pb-free, Halogen free, RoHS/WEEE compliant product

Rev 3 - April 2010

Page 1

Modulator

www.semtech.com

SX1231

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

Table of Contents

1.1.

1.2.

1.3.

2.1.

2.2.

2.3.

2.4.

Page

General Description ................................................................................................................................................ 8

Simplified Block Diagram ................................................................................................................................ 8

Pin and Marking Diagram................................................................................................................................ 9

Pin Description .............................................................................................................................................. 10

ESD Notice.................................................................................................................................................... 11

Absolute Maximum Ratings .......................................................................................................................... 11

Operating Range........................................................................................................................................... 11

Chip Specification ......................................................................................................................................... 12

Electrical Characteristics....................................................................................................................................... 11

2.4.1. Power Consumption ................................................................................................................................. 12

2.4.2. Frequency Synthesis ................................................................................................................................ 12

2.4.3. Receiver ................................................................................................................................................... 13

2.4.4. Transmitter ............................................................................................................................................... 14

2.4.5. Digital Specification ................................................................................................................................... 15

Chip Description.................................................................................................................................................... 16

3.1.

3.2.

3.3.

Power Supply Strategy.................................................................................................................................. 16

Low Battery Detector..................................................................................................................................... 16

Frequency Synthesis..................................................................................................................................... 16

3.3.1. Reference Oscillator ................................................................................................................................. 16

3.3.2. CLKOUT Output ........................................................................................................................................17

3.3.3. PLL Architecture ....................................................................................................................................... 17

3.3.4. Lock Time ..................................................................................................................................................18

3.3.5. Lock Detect Indicator................................................................................................................................ 18

3.4.

Transmitter Description ................................................................................................................................. 19

3.4.1. Architecture Description ........................................................................................................................... 19

3.4.2. Bit Rate Setting ........................................................................................................................................ 19

3.4.3. FSK Modulation ........................................................................................................................................ 20

3.4.4. OOK Modulation ....................................................................................................................................... 20

3.4.5. Modulation Shaping.................................................................................................................................. 21

3.4.6. Power Amplifiers ...................................................................................................................................... 21

3.4.7. Over Current Protection ........................................................................................................................... 21

3.5.

Receiver Description ..................................................................................................................................... 22

3.5.1. Block Diagram .......................................................................................................................................... 22

3.5.2. LNA - Single to Differential Buffer ............................................................................................................ 22

3.5.3. Automatic Gain Control ............................................................................................................................ 23

3.5.4. Quadrature Mixer - ADCs - Decimators.................................................................................................... 24

3.5.5. Channel Filter ........................................................................................................................................... 25

3.5.6. DC Cancellation ....................................................................................................................................... 26

3.5.7. Complex Filter - OOK ............................................................................................................................... 26

3.5.8. RSSI ......................................................................................................................................................... 26

Rev 3 - April 2010

Page 2

www.semtech.com

SX1231

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

3.5.9. Cordic ....................................................................................................................................................... 26

3.5.10. FSK Demodulator .................................................................................................................................... 27

3.5.11. OOK Demodulator .................................................................................................................................. 27

3.5.12. Bit Synchronizer ..................................................................................................................................... 29

3.5.13. Frequency Error Indicator....................................................................................................................... 29

3.5.14. Automatic Frequency Correction ............................................................................................................ 30

3.5.15. Optimized Setup for Low Modulation Index Systems ............................................................................. 31

3.5.16. Temperature Sensor ............................................................................................................................... 32

3.5.17. Timeout Function.................................................................................................................................... 32

Operating Modes .................................................................................................................................................. 33

4.1.

4.2.

Basic Modes.................................................................................................................................................. 33

Automatic Sequencer and Wake-Up Times .................................................................................................. 33

4.2.1. Transmitter Startup Time........................................................................................................................... 34

4.2.2. Tx Start Procedure ................................................................................................................................... 34

4.2.3. Receiver Startup Time.............................................................................................................................. 34

4.2.4. Rx Start Procedure ................................................................................................................................... 36

4.2.5. Optimized Frequency Hopping Sequences .............................................................................................. 36

4.3.

Listen mode................................................................................................................................................... 37

4.3.1. Timings ..................................................................................................................................................... 37

4.3.2. Criteria ...................................................................................................................................................... 38

4.3.3. End of Cycle Actions ................................................................................................................................ 38

4.3.4. RC Timer Accuracy .................................................................................................................................. 39

4.4.

5.1.

AutoModes .................................................................................................................................................... 40

Overview ....................................................................................................................................................... 41

Data Processing.................................................................................................................................................... 41

5.1.1. Block Diagram .......................................................................................................................................... 41

5.1.2. Data Operation Modes ............................................................................................................................. 41

5.2.

Control Block Description.............................................................................................................................. 42

5.2.1. SPI Interface............................................................................................................................................. 42

5.2.2. FIFO ......................................................................................................................................................... 43

5.2.3. Sync Word Recognition ............................................................................................................................ 44

5.2.4. Packet Handler ......................................................................................................................................... 45

5.2.5. Control ...................................................................................................................................................... 45

5.3.

Digital IO Pins Mapping................................................................................................................................. 45

5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 46

5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 46

5.4.

Continuous Mode .......................................................................................................................................... 47

5.4.1. General Description.................................................................................................................................. 47

5.4.2. Tx Processing........................................................................................................................................... 47

5.4.3. Rx Processing .......................................................................................................................................... 48

5.5.

Packet Mode ................................................................................................................................................. 48

5.5.1. General Description.................................................................................................................................. 48

Rev 3 - April 2010

Page 3

www.semtech.com

SX1231

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

5.5.2. Packet Format .......................................................................................................................................... 49

5.5.3. Tx Processing (without AES).................................................................................................................... 51

5.5.4. Rx Processing (without AES) ................................................................................................................... 52

5.5.5. AES .......................................................................................................................................................... 52

5.5.6. Handling Large Packets ........................................................................................................................... 54

5.5.7. Packet Filtering......................................................................................................................................... 54

5.5.8. DC-Free Data Mechanisms ...................................................................................................................... 56

Configuration and Status Registers ...................................................................................................................... 58

6.1.

6.2.

6.3.

6.4.

6.5.

6.6.

6.7.

6.8.

7.1.

7.2.

General Description ...................................................................................................................................... 58

Common Configuration Registers ................................................................................................................. 61

Transmitter Registers.................................................................................................................................... 64

Receiver Registers........................................................................................................................................ 65

IRQ and Pin Mapping Registers.................................................................................................................... 67

Packet Engine Registers............................................................................................................................... 69

Temperature Sensor Registers ..................................................................................................................... 72

Test Registers ............................................................................................................................................... 72

Crystal Resonator Specification .................................................................................................................... 73

Reset of the Chip .......................................................................................................................................... 73

Application Information ......................................................................................................................................... 73

7.2.1. POR.......................................................................................................................................................... 73

7.2.2. Manual Reset ............................................................................................................................................74

7.3.

8.1.

8.2.

8.3.

8.4.

9.1.

9.2.

Reference Design ......................................................................................................................................... 74

Package Outline Drawing.............................................................................................................................. 76

Recommended Land Pattern ........................................................................................................................ 76

Thermal Impedance ...................................................................................................................................... 77

Tape & Reel Specification............................................................................................................................. 77

RC Oscillator Calibration............................................................................................................................... 78

Listen Mode................................................................................................................................................... 78

Packaging Information .......................................................................................................................................... 76

Chip Revisions ...................................................................................................................................................... 78

9.2.1. Resolutions............................................................................................................................................... 78

9.2.2. Exiting Listen Mode .................................................................................................................................. 79

9.3.

9.4.

9.5.

OOK Floor Threshold Default Setting ........................................................................................................... 79

OCP Block..................................................................................................................................................... 79

AFC Control .................................................................................................................................................. 79

9.5.1. AfcAutoClearOn ....................................................................................................................................... 79

9.5.2. LowBetaAfcOn and LowBetaAfcOffset..................................................................................................... 79

10.

Revision History .................................................................................................................................................... 80

Rev 3 - April 2010

Page 4

www.semtech.com

SX1231

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

Index of Figures

Page

Figure 1. Block Diagram ................................................................................................................................................ 8

Figure 2. Pin Diagram .................................................................................................................................................... 9

Figure 3. Marking Diagram ............................................................................................................................................ 9

Figure 4. TCXO Connection ........................................................................................................................................ 16

Figure 5. Transmitter Block Diagram ........................................................................................................................... 19

Figure 6. Receiver Block Diagram ............................................................................................................................... 22

Figure 7. AGC Thresholds Settings ............................................................................................................................. 23

Figure 8. Cordic Extraction .......................................................................................................................................... 26

Figure 9. OOK Peak Demodulator Description ............................................................................................................ 27

Figure 10. Floor Threshold Optimization ..................................................................................................................... 28

Figure 11. Bit Synchronizer Description ...................................................................................................................... 29

Figure 12. FEI Process ................................................................................................................................................ 30

Figure 13. Optimized AFC (AfcLowBetaOn=1) ............................................................................................................ 31

Figure 14. Temperature Sensor Response ................................................................................................................. 32

Figure 15. Tx Startup, FSK and OOK .......................................................................................................................... 34

Figure 16. Rx Startup - No AGC, no AFC .................................................................................................................... 35

Figure 17. Rx Startup - AGC, no AFC ......................................................................................................................... 35

Figure 18. Rx Startup - AGC and AFC ........................................................................................................................ 35

Figure 19. Listen Mode Sequence (no wanted signal is received) .............................................................................. 37

Figure 20. Listen Mode Sequence (wanted signal is received) ................................................................................... 39

Figure 21. Auto Modes of Packet Handler ................................................................................................................... 40

Figure 22. SX1231 Data Processing Conceptual View ............................................................................................... 41

Figure 23. SPI Timing Diagram (single access) .......................................................................................................... 42

Figure 24. FIFO and Shift Register (SR) ..................................................................................................................... 43

Figure 25. FifoLevel IRQ Source Behavior .................................................................................................................. 44

Figure 26. Sync Word Recognition .............................................................................................................................. 45

Figure 27. Continuous Mode Conceptual View ........................................................................................................... 47

Figure 28. Tx Processing in Continuous Mode ............................................................................................................ 47

Figure 29. Rx Processing in Continuous Mode ........................................................................................................... 48

Figure 30. Packet Mode Conceptual View ................................................................................................................... 49

Figure 31. Fixed Length Packet Format ...................................................................................................................... 50

Figure 32. Variable Length Packet Format .................................................................................................................. 50

Figure 33. Unlimited Length Packet Format ................................................................................................................ 51

Figure 34. CRC Implementation .................................................................................................................................. 56

Figure 35. Manchester Encoding/Decoding ................................................................................................................. 56

Figure 36. Data Whitening ........................................................................................................................................... 57

Figure 37. POR Timing Diagram ................................................................................................................................. 73

Figure 38. Manual Reset Timing Diagram ................................................................................................................... 74

Figure 39. +13dBm Schematic .................................................................................................................................... 74

Figure 40. +17dBm Schematic .................................................................................................................................... 75

Figure 41. Package Outline Drawing ........................................................................................................................... 76

Rev 3 - April 2010

Page 5

www.semtech.com

推荐资源

有哪种CMOS技术可以做成微米级的芯片？: 有哪种CMOS技术可以做成微米级的芯片？ ...; 冯伟杰单片机

嵌入式技术基础与实践（基于摩托罗拉MCU，识货的来看看）: 嵌入式技术基础与实践,王宜怀,刘晓升编,清华大学出版社主要是面向freescale单片机设计。很好的一本书，现在书讲摩托罗拉单片机的很少。识货的下 24692...; fish001 嵌入式系统

这个速度无法理解，是否是正常的，环境是esp8266: import time,machine machine.freq(160000000) print(machine.freq()) time_start=time.ticks_ms() n=0 while(n < 10000): n=n+1 time_end=time.ticks_ms() print('time cost',time_e ......; wangshujun72 MicroPython开源版块

多功能限电保护器: 各位朋友：请大家帮我找个关于模拟电路的“多功能限电保护器”的毕业设计，模拟电路太简单了，做毕业设计字数好难弄够。...; sunguohong 单片机

物联网技术是什么？物联网技术都包含哪些？: 说起物联网，很多同学也都能说出一些特点，列举一些应用于自身的例子。随着网络科技的发展，5G时代的到来，物联网可以说已经逐渐渗透到了我们的生活中，休闲放松时，语音智能音箱放首歌，外出出 ......; 兰博无线连接

CCS6 XDS100V3能直接烧录2407的.out文件吗?: 手上只有 CCS6 CCS3.3 XDS100V2 XDS100V3。2407的工程文件是CCS3.3的，怎样才能烧录2407的.out文件。 ...; wellsking 微控制器 MCU

单片机stm32串口分析

　　stm32作为现在嵌入式物联网单片机行业中经常要用多的技术，相信大家都有所接触，今天这篇就给大家详细的分析下有关于stm32的出口，还不是很清楚的朋友要注意看看了哦，在最后还会为大家分享有些关于stm32的视频资料便于学习参考。　　什么是串口　　UART : Universal Asynchronous Receiver/Transmitter 通用异步收发器　　USART : Uni...[详细]
光伏直流熔断器如何申请UL248认证？

光伏直流熔断器是一种用于保护光伏电池组件、逆变器和直流负载的安全装置。为了保证其安全性和可靠性，需要通过UL248认证。在申请UL248认证之前，首先需要确定该产品符合UL标准的要求。UL标准可以通过官方网站或者相关资料获取。然后，需要选择一家符合要求的第三方测试机构-安可捷进行测试。测试公司会对光伏直流熔断器进行多项检测，包括电气性能、机械性能、绝缘性能等。测试结果需要符合UL标准...[详细]
目前电动汽车还存在哪些方面的安全隐患

随着购买新能源车型的消费者越来越多，电动车的安全性也成为了大家的焦点。尤其是在一系列电动车自燃事件之后，安全性这个话题也被推到了风口浪尖。那么电动车在电池方面存在着哪些隐患呢？一、冷却系统，新能源车型尤其是纯电动车型，是依靠电能作为补给。但电能并没有流入的冷却系统，所以在高温的条件下，电动车极容易发生自燃的事故。即便是现在很多新能源车型采用了水冷，但安全隐患依然存在。二、挤压碰撞，电...[详细]
电动汽车和燃油车它们各自的优势是什么

目前电动车来势汹汹，但只是表象而已。燃油车的地位依然无法撼动，电动汽车可以说在环保排放上有着得天独厚的优势，动力也不弱，远远超过同价位的燃油车，但是有很多缺点目前无法克服。电动车目前最大的瓶颈就是电池。电池能量密度低、容量衰减、充电困难以及安全系数是目前电动汽车发展遇到的主要问题。想要提高续航里程那么只需要加大电池容量即可，但是汽车不仅空间有限而且总质量也不宜过高，总质量过大则电耗也会加大...[详细]
同功率的电动汽车与燃油车相比谁的表现更好

同功率的电动机与内燃机，其扭矩大小是接近的。动力强需要高扭矩的支持，扭矩大小决定了一辆车加速快慢，也就是俗说的劲头大小。但是有时候同功率的电动机其扭矩并不会比内燃机高。例如比亚迪秦pro采用的电动机功率为110kw、最大扭矩为250Nm，而比亚迪秦pro采用的1.5T发动机，其最大功率为113kw，最大扭矩240牛米，可以说同功率的电机发动机扭矩也是接近的。又如大众1.4T发动机，最大功率...[详细]
莱迪思将举办关于最新小型、低功耗FPGA创新的网络研讨会

中国上海——2025年8月26日——莱迪思半导体公司，低功耗可编程器件的领先供应商宣布，公司将举办网络研讨会，探讨其基于屡获殊荣的Lattice Nexus™ FPGA产品系列的小型FPGA的最新扩展。本次直播将对新推出的莱迪思Certus™-NX和莱迪思MachXO5™-NX FPGA器件进行深入的技术介绍，这些新拓展的器件提供了高I/O密度、低功耗和增强的安全功能。莱迪思专家还将介...[详细]
苹果首款折叠 iPhone 曝料：配自研 C2 基带芯片

8 月 25 日消息，彭博社的马克・古尔曼昨日（8 月 24 日）发布博文，曝料称苹果将于 2026 年推出其首款折叠手机（下文简称 iPhone Fold），一方面会明显减少屏幕折痕，另一方面将搭载其自研的 C2 基带芯片，并采用无 SIM 卡设计、Touch ID 解锁，测试机有黑、白两色。苹果为尽量减少折痕的视觉影响，决定将屏幕触控感应层由 on-cell 技术改为 in-cell 技术...[详细]
SK 海力士开始量产 321 层 QLC NAND 闪存

8 月 25 日消息，SK 海力士公司宣布其 321 层 2Tb QLC NAND 闪存产品已完成开发并正式投入量产。这一成果标志着全球首次实现超过 300 层的 QLC 技术应用，为 NAND 存储密度树立了新的标杆。该公司计划在完成全球客户验证后，于明年上半年正式推出该产品。为提升新产品的成本竞争力，SK 海力士开发了一种容量为 2Tb 的设备，其容量是现有解决方案的两倍。为应对大容量 N...[详细]
萨里大学发明新型人工智能系统或将改变自动驾驶汽车在无GPS情况下的导航方式

据外媒报道，萨里大学（University of Surrey）的研究人员开发出一种无需依赖GPS即可在人口密集的城市地区精确定位设备位置的人工智能系统。该系统可将定位误差从734米缩小到22米以内，这对于自动驾驶汽车和救援车辆等技术的发展意义重大。图片来源：萨里大学在发表于《IEEE Robotics and Automation Letters》的论文中，研究人员介绍了PEn...[详细]
共享智慧的变革：研究人员开发群体智能机器人

在自动化技术突飞猛进的今天，机器人之间的协作已不再是科幻场景。试想这样的画面：数十台机器在仓库中搬运货物却互不干扰；在一个餐厅里，机器人能准确将菜品送至指定餐位；又或者在一个工厂里，机器人团队可以根据需求动态调整任务分工。（图片来源：ieeexplore.ieee.org）据外媒报道，国际研究团队依托基于ROS2的开源框架开发新系统，使多个机器人能以智能、灵活且安全的方式协同作业，...[详细]
DMA实现采样数据的直接搬运存储

尝试了下STM32的ADC采样，并利用DMA实现采样数据的直接搬运存储，这样就不用CPU去参与操作了。找了不少例子参考，ADC和DMA的设置了解了个大概，并直接利用开发板来做一些实验来验证相关的操作，保证自己对各部分设置的理解。我这里用了3路的ADC通道，1路外部变阻器输入，另外两路是内部的温度采样和Vrefint，这样就能组成连续的采样，来测试多通道ADC自动扫描了，ADC分规则转换和注入...[详细]
stm32直流电机驱动与测速学习总结

　　通过实验发现，定时器的一个通道控制一个pwm信号。　　在正式开始之前也可以参考这个视频学习资料　　(stm32直流电机驱动) 　　http://www.makeru.com.cn/live/1392_1218.html?s=45051 　　超声波雷达测距仪　　http://www.makeru.com.cn/live/15971_2626.html?s=45051 　　PWM驱动电机不...[详细]
一种新型的电气火灾监控报警系统应用探讨

引言　　据《中国火灾统计年鉴》显示，近十年的火灾事故中，电气火灾所占比例在30%以上，且呈逐年上升的趋势，已成为火灾的主要致灾因素，引起巨大的人财物损失。电气火灾产生的主要原因有短路、过载、接触电阻过大、静电等，其中接地性电弧短路是最危险也多发的电气火灾成因，主要是由于故障点接触不良，未被熔融而迸发出电或者电火花。而且发生电弧性短路的故障点阻抗较大，它的短路电流并不大(略大于300mA的电流...[详细]
是德科技携手新思科技运用AI进行射频设计迁移

是德科技将其电磁仿真器与新思科技的 AI 驱动射频设计迁移流程相结合，打造集成设计流程，助力从台积电 (TSMC) 的 N6RF+ 工艺技术迁移到 N4P 工艺技术。该迁移工作流程基于晶圆代工厂的模拟设计迁移 (ADM) 方法，旨在简化无源器件和设计组件的重新设计，使其符合先进的射频工艺规则。是德科技表示，该协作迁移工作流程充分利用了 N4P 工艺的性能提升，用于从 N6RF+ 迁移...[详细]
多电平逆变器的意思，需要高额定值的开关

多电平逆变器将DC信号转换成多电平阶梯波形。多电平逆变器的输出波形不是直接正负交替，而是多步交替。因为波形的平滑度与电压电平的数量成正比。因此，多电平逆变器将产生更平滑的波形。如前所述，较小步长的这一特性使其可用于实际应用。多电平逆变器是什么东西多电平逆变器的优势更好的电压波形:使用多电平逆变器，可以获得更好的电压波形。开关频率对于PWM操作可以进一步降低。使用低额定值设备的高电压...[详细]

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多