Data Sheet
STC705-706/706P-707-708-708T/S/R-813L
µ
P Supervisor Circuits
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Features
• Precision supply-voltage monitor
- 4.63V (STC706L/705, 813L, 708L/707)
- 4.38V (STC706M/706, 813M, 708M/708)
- 3.08V (STC706T, 813T, 708T)
- 2.93V (STC706S, 813S, 708S)
- 2.63V (STC706R, 813R/706P, 708R)
- 2.32V (STC706Z, 813Z, 708Z)
- 2.20V (STC706Y, 813Y, 708Y)
• 200ms reset pulse width
• Debounced TTL/CMOS-compatible manual-
reset input
• Independent watchdog timer 1.6sec time-out (not
available for STC707/708/708T/708S/R/Z/Y)
• Reset output signal:
- Active-low only (STC705/706/706T/S/R/Z/Y)
- Active-high only (STC813L/M/T/S/R/706P)
- Active-high and active-low (707/708/708T/S/R)
• Voltage monitor for power-fail or low battery warning
• Guaranteed RESET/RESET valid at V
CC
= 1.2V
Introduction
The STC706X/813X/708X family microprocessor
(µP) supervisory circuits are targeted to improve
reliability and accuracy of power-supply circuitry in
µP systems. These devices reduce the complexity and
number of components required to monitor power-
supply and battery functions.
The main functions are:
1. Asserting reset output during power-µp, power-
down and brownout conditions for µP system;
2. Detecting power failure or low-battery conditions
with a 1.25V threshold detector;
3. Watchdog functions (not for STC708x).
Applications
• Power-supply circuitry in µP systems
STC
1
Ver1.0
Data Sheet
STC705-706/706P-707-708-708T/S/R-813L
µ
P Supervisor Circuits
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Contents
Features ....................................................................................................................................................... 1
Block Diagram ............................................................................................................................................ 1
Introduction ................................................................................................................................................. 1
Pin Information ........................................................................................................................................... 4
Pin Configuration .............................................................................................................................. 4
Pin Description .................................................................................................................................. 4
Functional Description ................................................................................................................................ 5
Reset Output ...................................................................................................................................... 5
Watchdog Timer ................................................................................................................................ 5
Manual Reset ..................................................................................................................................... 5
Power-Fail Comparator ..................................................................................................................... 5
Function Reference Table .................................................................................................................. 6
Detailed Specifications ................................................................................................................................ 7
Absolute Maximum Ratings .............................................................................................................. 7
Recommended Operation Condition ................................................................................................. 7
DC Electrical Characteristics ............................................................................................................. 8
AC Electrical Characteristics ............................................................................................................. 9
Ordering Information ................................................................................................................................ 10
Mechanical Information ............................................................................................................................ 11
Notes ......................................................................................................................................................... 12
STC
2
Ver1.0
Data Sheet
STC705-706/706P-707-708-708T/S/R-813L
µ
P Supervisor Circuits
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Block Diagram
Figure 1. Block Diagram of STC706X/707, STC813X/706P
WDI
Watchdog
Transition Detector
Vcc
250uA
Watchdog Timer
WDO
Timebase for Reset
& Watchdog
MR
Reset Generator
Vcc
RESET *706X
(RESET *813X,706P)
V
RST
PFI
1.25V
PFO
Figure 2. Block Diagram of STC708X / 707
Vcc
250uA
MR
Reset Generator
Vcc
RESET
RESET
V
RST
PFI
PFO
1.25V
STC
3
Ver1.0
Data Sheet
STC705-706/706P-707-708-708T/S/R-813L
µ
P Supervisor Circuits
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Pin Information
Pin Configuration
Figure 3. Pin Configuration
STC706L/M/T/S/RESA
STC706L/M/T/S/REPA
8-Pin SOIC/8-Pin PDIP
MR
V
CC
GND
PFI
1
2
3
4
8
7
6
5
WDO
RESET
WDI
PFO
MR
V
CC
GND
PFI
STC813L/M/T/S/R/706PESA
STC813L/M/T/S/R/706PEPA
8-Pin SOIC/8-Pin PDIP
1
2
3
4
8
7
6
5
WDO
RESET
WDI
PFO
MR
V
CC
GND
PFI
STC708L/M/T/S/RESA
STC708L/M/T/S/REPA
8-Pin SOIC/8-Pin PDIP
1
2
3
4
8
7
6
5
RESET
RESET
NC
PFO
Top View
Pin Description
Table 1. Pin Description
P in Na m e
MR
Vcc
GND
PFI
PFO
Typ e
I
Power
Ground
I
O
Descr ip t ion
Ma n u a l-R eset : triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250
µA
pull-up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a
switch.
Power Su p p ly
G r ou n d R efer en ce for all signals
Power -Fa il Volt a ge Mon it or I n p u t: When PFI is less than 1.25V, PFO goes low. Connect PFI to
GND or Vcc when not used.
Power -Fa il O u t p u t : it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays
high.
Wa t ch d og I n p u t: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and
WDO goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables
the watchdog feature. The internal watchdog timer clears whenever reset is asserted. WDI is three-
stated, or WDI sees a rising or falling edge.
No C on n ect
O
R eset O u t p u t p u lses: low for 200ms when triggered, and stays low whenever Vcc is below the reset
threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low
to high. A watchdog timeout will not trigger RESET unless WDO is connected to MR.
Wa t ch d og O u t p u t : pulls low when the internal watchdog timer finishes its 1.6sec count and does
not go high again until the watchdog is cleared. WDO also goes low during low-line conditions.
Whenever Vcc is below the reset threshold, WDO stays low; however, unlike RESET, WDO does
not have minimum pulse width. As soon as Vcc rises above the reset threshold, WDO goes high
with no delay.
T h e inver se of R E SE T: active high. Whenever RESET is high, RESET is low.
WDI
I
NC
RESET
WDO
O
RESET
STC
O
4
Ver1.0
Data Sheet
STC705-706/706P-707-708-708T/S/R-813L
µ
P Supervisor Circuits
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Functional Description
The STCxxx family can assert reset output during power-up,
power-down and brownout conditions for uP system, detect
power failure or low-battery conditions with a 1.25V threshold
detector and have watchdog functions. Refer to Table 2 for
their individual features. The typical application see Figure 4.
Watchdog Timer
The watchdog circuit monitors the µP’s activity. If the µP does
not toggle the watchdog input (WDI) within 1.6sec and WDI is
not in high impedance, WDO goes low. As long as RESET is
asserted or the WDI input is in high impedance, the watchdog
timer will stay cleared and will not count. As soon as reset is
released and WDI is driven high or low, the timer will start
counting. Pulses as short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable
interrupt input (NMI) of a µP. When V
CC
drops below the reset
threshold, WDO will go low whether or not the watchdog timer
has timed out yet. Normally this would trigger an NMI
interrupt, but RESET goes low simultaneously, and thus
overrides the NMI interrupt. If WDI is left unconnected, WDO
can be used as a low-line output. Since floating WDI disables
the internal timer, WDO goes low only when V
CC
falls below
the reset threshold, thus functioning as a low-line output.
Reset Output
The supervisory circuits can assert reset for a microprocessor
during power-up, power-down and brownout to prevent code
execution errors.
On power-up, once V
CC
reaches about 1.2V, RESET is a
guaranteed logic low of 0.4V or less. As V
CC
rises, RESET stays
low. When V
CC
rises above the reset threshold, an internal timer
releases RESET after about 200ms. RESET pulses low whenever
V
CC
drops below the reset threshold (brownout condition). If
brownout occurs in the middle of a previously initiated reset
pulse, the pulse continues for at least another 140ms.
On power-down, once V
CC
falls below the reset threshold,
RESET stays low and is guaranteed to be 0.4V or less until Vcc
drops below 1V.
The STC813x and STC706P active-high RESET output is
simply the complement of the RESET output, and is guaranteed
to be valid with V
CC
down to 1.2V. Some µPs, such as Intel’s
80C51, require an active-high reset pulse.
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a
push-button switch. The switch is effectively debounced by
the 140ms minimum reset pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by any logic reset output.
Power-Fail Comparator
The power-fail comparator will send out a Low signal once
detects a voltage lowered than 1.25V. It can be used for various
purposes because its output and non-inverting input are not
internally connected. The inverting input is internally
connected to a 1.25V reference.
Figure 4. Typical Application Circuit
IN
DC Linear
Regulator
OUT
Vcc
RESET
µ
P Supervisory
Circuit
PFI
WDI
WDO
MR
PFO
Vcc
RESET
I/O Line
NMI
Interrupt
µ
P
STC
5
Ver1.0
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