SiP823/SiP824/SiP825
Vishay Siliconix
5-Pin
mP
Reset Circuits with Watchdog Timer and Manual Reset
FEATURES
D
D
D
D
D
D
D
D
Precision Power Supply Monitoring with
"1.5%
Accuracy
Low Quiescent Current: 3
mA
max.
Low Threshold Voltage Temperature Coefficient: 100 ppm max.
Guaranteed RESET Valid Dow to V
CC
= 1 V
Seven Reset Threshold Options
Small SOT23-5 Packages
No External Components
Power Supply Transient Immunity
APPLICATIONS
D
Portable Intelligent Electronics
D
Computers and Controllers
D
Automotive Electronics
D
Critical
mP/mC
Power Supply Monitoring
DESCRIPTION
The SiP823/SiP824/SiP825 series are
mProcessor
supervisory circuits in a 5-pin SOT23 package, that combine
the functions of power supply and
mProcessor
monitoring.
If the power supply voltage drops, or has been, below a safe
level or the
mProcessor
shows signs of problematic inactivity,
the circuit will generate a reset signal at it’s output.
The SiP823 and SiP825 have an input to accommodate
manual reset.
Seven pre-programmed reset threshold voltage levels are
available as standard options.
Specially configured options are available upon request,
allowing for further customization of reset voltage, reset
time-out, and watchdog time-out periods.
The SiP823 has a reset output that is “active low” and the
SiP824 and SiP825 have complementary outputs for both
“active high” and “active low” resets. Both output drives are
push/pull configurations.
Space saving SOT23-5 packages and low quiescent current
make this family of products ideally suited for portable battery
operated equipment.
These circuits fully ignore fast negative V
CC
transients and
have valid reset output signals with power supply levels down
to 1 V.
PACKAGING AND PIN DEFINITION
SOT-23
RESET
GND
MR
1
2
3
5
V
CC
RESET
GND
4
WDI
RESET
1
2
3
SOT-23
5
V
CC
RESET
GND
4
WDI
RESET
1
2
3
SOT-23
5
V
CC
SiP823
SiP824
SiP825
4
MR
Top View
Top View
See page 2 for ordering and marking information.
Top View
TYPICAL APPLICATION CIRCUIT
V
CC
V
CC
RESET
V
CC
RESET
mProcessor
I/O
GND
SiP823
MANUAL
RESET
MR
GND
WDI
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
1
SiP823/SiP824/SiP825
Vishay Siliconix
ORDERING INFORMATION
SiP823
SiP824
SiP825
Watchdog time-out Period
Default: 1.76 Sec
Reset time-out Period
Default: 210 mS
Threshold Voltage Options
L: 4.63 V
M: 4.38 V
T: 3.08 V
S: 2.93 V
R: 2.63 V
Z: 2.32 V
Y: 2.19 V
Please contact your local Vishay Semiconductor Sales Office for information on
customization of reset voltage, reset time-out, and watchdog time-out options.
x EU x x DT-TR1
MARKING INFORMATION
SiP823
SiP823LEU
SiP823MEU
SiP823TEU
SiP823SEU
SiP823REU
SiP823ZEU
SiP823YEU
AAxxx
ABxxx
ACxxx
ADxxx
AExxx
AGxxx
AHxxx
SiP824LEU
SiP824MEU
SiP824TEU
SiP824SEU
SiP824REU
SiP824ZEU
SiP824YEU
SiP824
AIxxx
AKxxx
ALxxx
AMxxx
ANxxx
AOxxx
APxxx
SiP825LEU
SiP825MEU
SiP825TEU
SiP825SEU
SiP825REU
SiP825ZEU
SiP825YEU
SiP825
ARxxx
ASxxx
ATxxx
AVxxx
AWxxx
AXxxx
AYxxx
Last two characters denote date code.
ABSOLUTE MAXIMUM RATINGS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Supply Voltage
All Other Pins
Input/Output Current, All Pins
Operating Temperature Range
Storage Temperature Range
Junction Temperature Range
Power Dissipation (T
A
v
70_C)
SOT-23 (Derate 4 mW/_C above 70_C)
Symbol
V
CC
V
MAX
I
IN(max)
T
A
T
stg
T
J
P
D
Limit
−0.3
to 6.0
−0.3
to (V
CC
+ 0.3)
20
−40
to 85
−65
to 150
−40
to 125
310
Unit
V
mA
_C
mW
Notes
a. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
www.vishay.com
2
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
SiP823/SiP824/SiP825
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Supply Voltage
Supply Current (No Load)
RESET Threshold
Threshold Hysteresis
RESET Threshold
Temperature Coefficient
V
OL
V
OH
V
OL
V
OH
V
CC
to RESET Delay
RESET Time-out Period
T
D1
T
D2
Sip82_L/M/J: V
CC
t
V
TH
, I
SINK
= 1.2 mA
Sip82_R/S/T/Y/Z: V
CC
t
V
TH
, I
SINK
= 0.5 mA
V
CC
u
V
TH
, I
SOURCE
= 0.5 mA
Sip82_L/M/J: V
CC
u
V
TH
, I
SINK
= 1.2 mA
Sip82_R/S/T/Y/Z: V
CC
u
V
TH
, I
SINK
= 0.5 mA
V
CC
t
V
TH
, I
SOURCE
= 0.5 mA
V
CC
= V
TH
−
100 mV
140
0.8 V
CC
40
210
280
mS
mS
0.8 V
CC
0.5
0.4
Limits
Min
a
Typ
b
Max
a
Unit
Symbol
V
CC
I
CC
V
TH
V
TH(hys)
T
A
=
−40_C
to 85_C, Typical Values @ T
A
= 25_C
1
V
CC
= V
TH
+ 10%
T
A
= 25_C
T
A
= 25_C
V
TH
−1.5%
0.4
40
5.5
10.0
3.0
V
TH
1.5%
V
mA
V
%V
TH
PPM/_C
0.5
0.4
V
RESET Output Voltage
p
g
RESET Output Voltage
p
g
Watchdog Input (SiP823/SiP824)
Watchdog Time-out Period
W
D1
Pulse Width
W
DI
Input Voltage
c
W
DI
Input Current
t
WD
t
WDI
V
IL
V
IH
I
IL
I
IH
V
IL
= 0.4 V, V
IH
= 0.8 V
CC
V
CC
= V
TH
+ 20%
W
DI
= 0 V
W
DI
= V
CC
= 5 V
1.12
50
0.7
0.8 V
CC
−15
−8
8
15
1.76
2.40
S
nS
V
mA
Manual Reset Input (SiP823/SiP825)
MR Pulse Width
MR Input Voltage
MR Noise Immunity
(Pulse Width with No RESET)
MR to RESET Delay
MR Pull-Up Resistance
t
MR
80
t
MR
V
IL
V
IH
V
CC
= V
TH
+ 20%
1.0
0.7
0.8 V
CC
100
500
120
kW
mS
V
nS
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
c. W
DI
is internally serviced within the watchdog period if W
DI
is left unconnected.
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
3
SiP823/SiP824/SiP825
Vishay Siliconix
PIN DESCRIPTION
SiP823
1
2
N/A
3
SiP824
1
2
3
N/A
SiP825
1
2
3
4
Name
RESET
GND
RESET
MR
Ground
Description
RESET is active low. This pin has a push/pull output.
RESET is active high. This pin has a push/pull output.
Manual RESET. Active low. Pulling this pin low forces a RESET. After a low to high transition RESET
remains asserted for exactly one RESET timed period. This pin is internally pulled high. If this function is
unused it can be left open or tied to V
CC.
Watchdog Input. Any transition on this pin will RESET the watchdog timer. If this pin remains high or low
for longer than the watchdog interval, a RESET is asserted. Float or tristate this pin to disable the
watchdog feature.
Positive power supply. A RESET is asserted after this voltage drops below a predetermined level. After
V
CC
rises above that level, RESET remains asserted until the end of the RESET time-out period.
4
5
4
5
N/A
5
W
DI
V
CC
TIMING DIAGRAMS
V
TH
V
TH
V
CC
t
D2
RESET
50%
t
D1
50%
t
D2
RESET
50%
t
D1
50%
Figure 1.
RESET Timing Diagram
V
TH
V
DD
t
D2
t
D2
RESET
B
t
WD
WDI
Figure 2.
Watchdog Timing Diagram
www.vishay.com
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
4
SiP823/SiP824/SiP825
Vishay Siliconix
DETAILED DESCRIPTION
An active signal on a microprocessor (mP) RESET input starts
the
mP
in a know state. The SiP823/SiP824/SiP825
mP
supervisory circuits assert a RESET signal to prevent code
execution errors during power-up, power-down and brown-out
conditions.
The SiP823/SiP824/SiP825 also monitors the
mP’s
health by
checking for problematic inactivity at its W
DI i
input.
RESET Output
A RESET will be asserted for the specified RESET time-out
period (t
D2
), if any of three conditions are present:
1) V
CC
drops below the threshold voltage (V
TH
)
2) The MR pin is pulled low
3) The watchdog timer does not detect a transition within the
watchdog interval (t
WD
) and the watchdog input is not left
floating.
The RESET output will remain asserted for the specified
time-out period (t
D2
) after:
1) V
CC
rises above the RESET threshold (V
TH
)
2) MR goes high.
Manual RESET Input
mP
based products often require a manual RESET capability,
which can be activated by manual intervention or external logic
circuitry.
A logic low at the MR pin of the SiP823/SiP824/SiP825 asserts
a RESET signal. RESET remains asserted while MR is low
and for a period (t
D2
) after it returns high.
MR has an internal 100-kW pull-up resistor, so it can be left
floating when not activated. This input can be driven with
CMOS logic levels or with open drain devices. The input is
internally de-bounced to reject fast input transients.
Watchdog Input (SiP823/SiP824)
The SiP823/SiP824 have a watchdog input (WDI), that
monitors the
mP’s
activity. If the
mP
does not toggle the
watchdog input within the watchdog time-out period (t
WD
),
RESET is asserted. The internal RESET timer is cleared by
either a RESET pulse or by toggling WDI.
WDI detects pulses as short as 50 nS. While RESET is
asserted, the timer remains cleared. As soon as RESET is
released the timer starts counting (Figure 2).
The watchdog timer can be disabled by leaving WDI open or
by three stating the connected driver. As soon as the WDI input
is driven either high or low, the watchdog function resumes with
the watchdog timer set to zero.
WDI Input Current
The watchdog input pin (WDI) typically sources or sinks 8
mA
when driven high or low.
As a result, the power dissipation at the WDI input is
independent of duty cycle. When the WDI pin is left floating or
tri-stated, the power supply current is less than 3
mA.
Transient Rejection
The SiP823/SiP824/SiP825 family has good immunity for
negative going transients on the V
CC
line.
The smaller the duration of the transient, the larger the
amplitude can be without triggering RESET.
The “Transient Rejection” graph below shows the relation
between transient amplitude and allowable transient duration,
without triggering RESET.
The value on the horizontal scale represents the portion of the
amplitude of the transient that is exceeding the V
TH
level.
RESET Output State at Low V
DD
With V
CC
voltage on the level of MOS transistor thresholds
(t1.0 V), the RESET output of the SiP823/SiP824/SiP825
may become undefined. For outputs that are active low
(RESET), a resistor placed between RESET and GND on the
order of 100 kW will ensure that the RESET output stays low
when the V
CC
drops below the MOS transistor threshold. In a
like manner, a resistor placed between RESET and V
CC
will
ensure the correct state for active high RESET outputs.
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
5
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