a. Device mounted with all leads soldered or welded to PC board.
b. Derate 20 mW/_C above 70_C
c. Derate 23.5 mW/_C above 70_C
New Product
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25 V to 5.5 V
Enable Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V
Operating Temperature Range T
A
. . . . . . . . . . . . . . . . . . . . . . . .
−40
to 85_C
Operating Temperature Range T
J
. . . . . . . . . . . . . . . . . . . . . . .
−40
to 125_C
SPECIFICATIONS
Test Conditions Unless Specified
p
Parameter
Regulators
Output Voltage Accuracy
Output Voltage
Temperature Coefficient
Line Regulation
f
Load Regulation
V
IN
= V
OUT
+ 1 V to 5 5 V
5.5
I
OUT
= 100
mA
to 150 mA (LDO 1 and 2)
I
OUT
= 100
mA
to 300 mA (LDO 2)
I
OUT
= 150 mA (LDO 1 and 2)
Dropout Voltage
g
V
DROP
I
OUT
= 300 mA (LDO 2)
I
OUT1
= I
OUT2
= 0
mA
Ground Pin Current
I
G
I
OUT1
= I
OUT2
= 0
mA
I
OUT1
= 150 mA, I
OUT2
= 300 mA
V
EN
t
0.4 V
Sequence Time
Delay
d
t
SEQ
C
BP
= 0.01
mF
f = 1 kHz, C
OUT
= 1
mF,
C
BP
= 10 nF
f = 20 kHz, C
OUT
= 1
mF,
C
BP
= 10 nF
Room
Room
Output Voltage Noise
Ripple Rejection
From Nominal V
OUT
Room
Full
Room
Room
Full
Room
Room
Room
Full
Room
Full
Room
Full
Room
Full
Room
70
30
60
40
60
2.0
ms
mVrms
dB
48
240
120
−0.3
−0.6
0.2
−1
−2
40
0.2
0.3
0.6
1.0
1.5
190
250
340
420
65
80
mA
mV
%
1
2
%
ppm/_C
Limits
Temp
a
Min
b
Typ
c
Max
b
Unit
Symbol
V
IN
= V
OUT
+ 1 V
f
, C
OUT
= 1
mF,
I
OUT
= 100
mA,
T
A
= 25
_C
Inputs
EN,
EN SW Input Voltage
EN,
EN SW Input Current
SET Pin Threshold Voltage
SET Pin Current Source
V
IL
V
IH
I
IL
I
IH
V
TH
(set)
Logic Low
Logic High
V
IL
t
0.6 V
V
IH
u
1.8 V
POR = High
V
SET
= 0 V
Full
Full
Room
Room
Room
Room
0.75
1.8
−1
−1
0.01
0.01
1.25
1.25
1.75
1
1
0.6
V
mA
V
mA
Power On Reset (POR) Output
Threshold
Output Voltage
Leakage Current
V
THL
V
THH
V
OL
I
POR
% of Nominal V
OUT2
I
L
= 250
mA
POR = High
Room
Room
Room
Room
−1
0.02
0.01
90
96
0.1
1
%
V
mA
Driver (DRV) Output
Output Voltage
Leakage Current
www.vishay.com
V
OL
I
L
= 150 mA
I
DRV
= 0 mA, V
DRV
= 5.5 V, SW = 0 V
Full
Room
−1
0.2
0.01
0.6
1
V
mA
2
Document Number: 73190
S-50922—Rev. C, 09-May-05
SiP2213
New Product
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Protection
Current Limit
Thermal Shutdown
Temperature
Thermal Hysteresis
I
IL
V
OUT1
= 0 V
V
OUT2
= 0 V
Room
Room
Room
Room
150
300
280
450
165
25
460
700
mA
Vishay Siliconix
Limits
Temp
a
Min
b
Typ
c
Max
b
Unit
Symbol
V
IN
= V
OUT
+ 1 V
f
, C
OUT
= 1
mF,
I
OUT
= 100
mA,
T
A
= 25
_C
_C
C
Notes
a. Room = 25_C, Full =
−40
to 85_C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Timing is measured from 90% of LDO #1’s final value to 90% of LDO #2’s final value.
e. Guaranteed by design.
f.
For higher output of the regulator pair.
g. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V
IN
does not drop below 2.25 V. When V
OUT(nom)
is less than 2.25 V, the output will be in regulation when 2.25 V
−
V
OUT(nom)
is
greater than the dropout voltage specified.
FUNCTIONAL BLOCK DIAGRAM
V
IN
EN
LDO #1
V
OUT1
LDO #2
SET
BP
Reference
POR
DLY
V
OUT2
POR
DRV
SW
SW
LOGIC
GND
GND
SW
Fixed Voltage Version
V
IN
EN
1
LDO #1
V
OUT1
ADJ
1
LDO #2
V
OUT2
ADJ
2
POR
DLY
POR
SET
BP
Reference
DRV
SW
SW
LOGIC
GND
GND
SW
Adjustable Voltage Version
Document Number: 73190
S-50922—Rev. C, 09-May-05
www.vishay.com
3
SiP2213
Vishay Siliconix
New Product
PIN CONFIGURATIONS AND ORDERING INFORMATION
PowerPAK MLP33-10
V
IN
EN
BP
SW
SET
1
2
3
4
5
10
9
8
7
6
V
OUT1
V
OUT2
POR
DRV
GND
V
OUT1
V
OUT2
POR
DRV
GND
10
9
8
7
6
1
2
3
4
5
V
IN
EN
BP
SW
SET
Exposed Pad
VOLTAGE OPTIONS
Voltage
Adj
1.5
1.6
1.8
1.9
2.0
2.1
2.5
2.6
2.7
2.8
2.85
2.9
3.0
3.1
1
2
3
4
EN
1
NC
BP
ADJ
1
Code (x,z)
A
F
W
G
Y
H
E
J
K
L
M
N
O
P
Q
R
S
T
U
V
Top View
Bottom View
PowerPAK MLP44-16
V
OUT2
V
OUT1
V
IN
15
V
IN
16
13
POR
DRV
ADJ
2
GND
SW
12
11
10
9
8
GND
14
3.2
3.3
3.4
3.5
3.6
7
GND
6
SET
5
SW
ORDERING INFORMATION
Part Number
SiP2213DMP-XZ-T1
SiP2213DLP-AA-T1
X: Output 1 voltage code
Z: Output 2 voltage code
Temp
Range
−40
to 85_C
40
Package
PowerPAK MLP33-10
PowerPAK MLP44-16
Marking
13XZ
13AA
Bottom View
PIN DESCRIPTION
Pin Number
MLP33-10
1
2
1
2
3
4
5
6
3
5
4
6
7, 8
9
10
7
8
9
10
11
12
13
14
MLP44-16
15, 16
Name
V
IN
EN
EN
NC
BP
SW
ADJ
1
SET
GND
GND
SW
ADJ
2
DRV
POR
V
OUT2
V
OUT1
Enables both LDO outputs.
Enables both LDO outputs.
No Connect
Bypass for noise reduction
Control for open drain output
Feedback connection for LDO #1
Function
Input voltage for the power MOSFETs and their gate drive
Connection for external capacitor to delay POR
Ground
Ground for the internal n-channel MOSFET switch
Feedback connection for LDO #2
Open drain output
Power ON reset output
Output of LDO #2
−
300 mA
Output of LDO #1
−
150 mA
The exposed pad on both packages must be connected externally to the GND pin.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
