SiP12202
New Product
Vishay Siliconix
Synchronous Step Down Controller
DESCRIPTION
SiP12202 is a synchronous step down controller
designed for use in dc-dc converter circuits requiring
output currents as high as 10 amperes. SiP12202 is
designed to require a minimum number of external
components, simplifying design and layout. It accepts
input voltages from 2.7 V to 5.5 V, providing an adjust-
able output with voltage ranging from 0.6 V to 5.5 V.
SiP12202 includes a combination Compensation/
Shutdown pin. Protection features include undervolt-
age lockout, Power Good output, output current limit,
and thermal shutdown.
SiP12202 is available in a lead (Pb)-free MLP-33-10
package and is specified to operate over the range of
- 40 °C to 85 °C.
FEATURES
• 2.7 V to 5.5 V Input Voltage Range
• Adjustable Output Voltage - 0.6 to 5.5 V
• For Converter loads up to 10 A
• High efficiency - 93%
• Uses High Side P-Channel MOSFET
• Uses Low Side N-Channel MOSFET
• 500 kHz operation
• Internal Soft Start
• Power Good Indication
• Shutdown Pin
• Output Current Limit
• Minimum External Components
• MLP33-10 Package
APPLICATIONS
•
•
•
•
•
Distributed Power
Desktop & Notebook Computers
Battery Operated Equipment
Point of Load Regulation
DSP Cores
TYPICAL APPLICATION CIRCUIT
VIN
VIN
VIN
DH
LX
Power Good
Compensation/
Shutdown
PG
DL
COMP/SD
VOUT
FB
AGND P
AGNDPGND
GND
GND
Document Number: 73542
S-52083–Rev. A, 10-Oct-05
www.vishay.com
1
SiP12202
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
V
IN
, LX to GND
FB, P
G
, Comp/SD to GND
Power Dissipation
a, b
Maximum Junction Temperature
Storage Temperature
Notes
a. Device mounted with all leads soldered or welded to PC board
b. Derate 14 mW/°C above + 85 °C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
Limit
6
- 0.3 to 6
560
125
- 55 to + 150
Unit
V
mW
°C
New Product
RECOMMENDED OPERATING RANGE
Parameter
Input Voltage Range
Output Voltage Adjustment Range
Operating Temperature Range
Limit
2.7 to 5.5
0.6 to 5.5
- 40 to + 85
Unit
V
°C
SPECIFICATIONS
Parameter
Controller
Input Voltage
Quiescent Current
Switching Oscillator Frequency
Oscillator Ramp Amplitude
Feedback Voltage
FB input Bias Current
Transconductance
Soft Start
Inputs and Outputs
SD Input Voltage
Shutdown Current
MOSFET Drivers
Break-before-make-time
Highside Driver
Output Voltage
On resistance
Rise time - PFET Turn On
Fall time - PFET Turn Off
Lowside Driver
Output Voltage
On resistance
Rise time - NFET Turn On
Fall time - NFET Turn Off
V
DL
R
DSLH
R
DSLL
t
rL
t
fL
V
IN
= 4.5 V
V
IN
= 4.5 V
V
IN
= 5 V, C
L
= 2.7 nF
V
IN
= 5 V, C
L
= 2.7 nF
4.5
5.5
0.85
83
6.6
8.2
1.4
V
Ω
Ω
ns
V
DH
R
DSHH
R
DSHL
t
rH
t
fH
V
IN
= 4.5 V
V
IN
= 4.5 V
V
IN
= 5 V, C
L
= 2.7 nF
V
IN
= 5 V, C
L
= 2.7 nF
4.5
1.3
2.8
64
8
1.9
4.4
V
Ω
Ω
ns
t
BBM
30
ns
V
IL
I
IL
30
0.15
60
V
µA
f
OSC
∆V
OSC
V
FB
I
FB
GM
2
4
T
A
= 25 °C
0.591
0.585
V
IN
Non Switching
400
2.7
0.6
500
1
0.600
0.609
0.615
100
5.5
1
600
V
mA
kHz
V
V
nA
mA/V
ms
Symbol
Test Condition Unless Specified
V
IN
= 5.0
Limits
-40 to 85°C
Min
a
Typ
b
Max
a
Unit
www.vishay.com
2
Document Number: 73542
S-52083–Rev. A, 10-Oct-05
SiP12202
New Product
SPECIFICATIONS
Parameter
Protection
Under voltage lockout
UVLO-Hysteresis
Power Good
P
G
Output Voltage
P
G
Leakage Current
P
G
Voltage Threshold
P
G
Threshold Hysteresis
Over Current Limit
Thermal Shutdown Temperature
Thermal Hysteresis
MOSFET On Voltage Sense Threshold
V
DL
With respect to V
IN
-335
Rising
165
20
-300
-265
°C
°C
mV
V
PGOL
I
PGOL
V
ETH
V
EH
I
SINK
= 0.5 mA
70
5
0.4
1
V
µA
%V
OUT
%V
OUT
V
UVLO
Rising
2.3
2.4
0.10
2.5
V
Symbol
Test Condition Unless Specified
V
IN
= 5.0
Limits
-40 to 85°C
Min
a
Typ
b
Max
a
Unit
Vishay Siliconix
NOTES:
a) The algebriac convention whereby the most negative value is a minimum and the most positive a maximum.
b) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
PIN CONFIGURATION
PIN DESCRIPTION
Part Number
1
2
3
4
5, 10
6
7
8
9
Name
COMP/SD
FB
AGND
P
G
V
IN
DL
PGND
LX
DH
Feedback input
Analog Ground
Indicates that the output voltage is in regulation
Input voltage for the power MOSFETs and their gate drive
Lowside gate drive
Power Ground
Connection for the inductor node
Highside gate drive
Function
Combination Compensation and Shut down pin
ORDERING INFORMATION
Part Number
SiP12202DM-T1-E3
Eva Kit
SiP12202DB
Temperature Range
-40 to 85 °C
Temperature Range
-40 to 85 °C
Package
MLP33-10
Board
Surface Mount
Document Number: 73542
S-52083–Rev. A, 10-Oct-05
www.vishay.com
3
SiP12202
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
SiP12202
New Product
0.45 V
PG
FB
Vin
Vin
UVLO
Over Temp
Over Voltage
DH
Soft Start
Shut
Down
Over Current
Sense
Comp
LX
FB
GM
PWM Comp
0.6 V
OSC
500KHz
∆Vosc
Gate Control
Logic
BBM
Vin
DL
Pgnd
SD/Comp
Agnd
DETAILED OPERATIONAL DESCRIPTION
Enable/ON State:
The COMP/SD pin has 10 µA pull up current to ensure
auto startup as soon as the pin is released by the
external pull down MOS. When the internal reference
is ready, there will be a clamp current applied at
COMPSD; this is to ensure the COMPSD pin will not
go below 600 mV inadvertently due to the amplifier
excursion or noise. The COMPSD has to go above 600
mV to enable the chip fully.
Disable/Shutdown/Off State
To disable the chip, the COMP/SD pin has to pulled
below 150 mV typically and the external pull down
MOSFET has to be able to sink at least 250 µA. Once
the pin reaches a voltage below the 150 mV level, the
chip will go into shutdown mode with only essential
curcuitry alive and the current bias of the chip will be
cut down to 30 µA level typically. Both High Side and
Low Side Gates are off.
UVLO:
The chip enters into Under Voltage Lockout when V
IN
is below 2.3 V (typical). Both High Side Gate and Low
Side Gate will be turned off. The chip will go out of
UVLO mode when V
IN
is above 2.4 V (typical).
Soft Start:
Once the chip is out of shutdown and UVLO mode the
soft start is initiated. The soft start is done accom-
plished by ramping up the internal reference. During
soft start mode the chip can not enter into fault mode.
If there is an over current condition (current limit condi-
tion), the High Side Gate will be turned off and the Low
Side will be turned on. Once the soft start timing
elapses, the chip enters into a normal state of opera-
tion.
Output Over Voltage State:
When the Output voltage goes above 1.083 times
nominal Output Voltage, the High Side Gate will be
turned off and the Low Side Gate will be on. The con-
dition will persist until the Output voltage drops below
the trigger voltage minus a hysteresis.
Output Over Current State:
The SiP12202 will enter a cycle by cycle over current
condition when the voltage on the LX pin falls below
V
IN
by 300 mV. During the over current condition the
High Side MOSFET is turned off for the duration of the
existing cycle. At the beginning of the next cycle the
High Side MOSFET turns on and the LX voltage is
measured again. If the over current condition still
exists, the High Side MOSFET is turned off again. This
is repeated seven consecutive times after which the IC
will go into a fault state. If the over current condition is
removed before seven consecutive cycles the IC
reverts to normal operating mode.
Document Number: 73542
S-52083–Rev. A, 10-Oct-05
www.vishay.com
4
SiP12202
New Product
Fault State:
The IC can only enter into Fault mode after the soft
start mode has ended and seven consecutive over cur-
rent condition cycles has occurred. Once it enters the
Fault state, with the High Side MOSFET turned off and
the Low Side MOSFET turned on, any occurring over
current condition will be ignored. The Fault State will
last for seven soft start cycles. After which the IC will
enter Soft Start mode. If the over current condition is
removed the IC will operate normally, otherwise the
over current sequence is repeated. This fault scheme
minimizes thermal stress on the external power MOS-
FET switches
Over Temperature:
When the temperature of the chip goes above 165 °C,
the chip enters into over temperature shutdown. The
High Side gate will be off and the Low Side gate will be
on. Only system monitor circuitry will be active. Once
the temperature of the chip drops below 145 °C, the
chip enters into the normal operation mode.
Power Good:
Power Good State: When the output is above 0.75
times nominal output voltage, the PC signal will be
high to indicate that the output voltage is available for
external use. The PG pin requires a pull up resistor.
Setting the Output Voltage:
An output voltage between 0.8 V and (0.9 V x V
IN
) 0.6
V and V
IN
and can be configured by connecting FB pin
to a resistive divider between the output and GND.
Select resistor R2 in the 1 kΩ to 10 kΩ range. R1 is
then given by:
R
1
= R
2
FREQUENCY (kHz)
Vishay Siliconix
TYPICAL CHARACTERISTICS
100
95
90
Vout =
3.3
V
EFFICIENCY (%)
85
80
75
70
65
60
55
Vout = 2.5 V
Vin = 5.0 V
50
0
2
4
6
8
10
LOAD CURRENT (A)
EFFICIENCY vs LOAD CURRENT
600
550
Vin = 5.0 V
500
450
Vin = 2.7 V
400
-45
-10
25
60
95
130
TEMPERATURE (°C)
OSCILLATOR FREQUENCY Vs TEMPERATURE
0.615
(
V
V
OUT
FB
−1
)
VOLTAGE ( V)
0.605
Vin = 2.7 V to 5.0 V
where VFB = 0.6 V.
VOUT
0.595
R1
FB
R2
0.585
-45
-10
25
60
95
130
TEMPERATURE (°C)
FEEDBACK THRESHOLD Vs TEMPERATURE
0.6 V
Document Number: 73542
S-52083–Rev. A, 10-Oct-05
www.vishay.com
5
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