SiI 141B PanelLink Digital Receiver
General Description
The SiI 141B uses PanelLink Digital technology to support displays
ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements. These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
®
May 2001
Features
•
•
•
•
•
•
•
•
Scaleable Bandwidth: 25-86 MHz (VGA to High
Refresh XGA)
Low Power: 3.3V core operation & power-down mode
Automatic power down when clock is inactive
High Skew Tolerance: 1 full input clock cycle (15ns at
65 MHz)
Pin-compatible with SiI 101, SiI 141
Sync Detect: for Plug & Display “Hot Plugging”
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&D
TM
and DFP)
SiI 141B Pin Diagram
24-bit Input Data for 1-pixel/clock mode
8-bit Channel 2 Data
1-pixel/clock
8-bit Channel 1 Data
1-pixel/clock
8-bit Channel 0 Data
1-pixel/clock
18-bit Even Data for 2-pixel/clock mode
6-bit Odd Channel 0
Data 2-pixel/clock
ODCK
GND
VCC
Q19
Q18
6-bit Even Channel 2
Data 2-pixel/clock
Q17
Q16
Q15
Q14
Q13
Q12
Q11
6-bit Even Channel 1
Data 2-pixel/clock
OGND
OVCC
Q10
Q9
Q8
Q7
Q6
Q5
18-bit Odd Data for 2-pixel/clock mode
DE
Q20
Q21
Q22
Q23
OGND
Q24
6-bit Odd Channel 1
Data 2-pixel/clock
OVCC
Q25
VCC
Q26
Q27
Q28
Q29
6-bit Odd Channel 2
Data 2-pixel/clock
Q30
Q31
Q32
Q33
Q34
Q35
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
75
68
62
71
66
72
74
77
61
63
69
64
67
76
65
70
73
78
79
80
20
19
18
17
16
15
14
13
Q4
Q3
Q2
Q1
Q0
OVCC
VSYNC
OGND
HSYNC
GND
CTL3
CTL2
CTL1
SCDT
DFO
PIXS
OGND
PDO
PD
RESERVED
GENERAL
PURPOSE
CONTROL
CONTROL
SiI141B
80-Pin TQFP
(Top View)
12
11
10
9
8
7
6
5
4
3
2
1
AGND
AGND
HSYNC_DEJTR
DIFFERENTIAL SIGNAL
OCK_INV
PGND
GND
AVCC
AVCC
EXT_RES
RXC+
PVCC
VCC
RX2+
RX1+
RX0+
RXC-
RX2-
RX1-
RX0-
ST
MISC.
Subject to Change without Notice
6-bit Even Channel 0
Data 2-pixel/clock
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SiI 141B
Functional Block Diagram
ST
PIXS
DFO
OCK_INV
PDO
HSYNC_DEJTR
EXT_RES
Termination
Control
8
RX2+
RX2-
VCR
DATA
RECOVERY
CH2
CLT3
CLT2
DE2
24/36
SiI-DS-0037-C
Q[35:0/23:0]
ODCK
DE
HSYNC
PANEL
INTER-
FACE
LOGIC
8
RX1+
RX1-
VCR
DATA
RECOVERY
CH1
INTER-
CHANNEL
SYNC.
CLT1
DECODER PLL_SYNC
DE1
VSYNC
SCDT
8
RX0+
VCR
RX0-
DATA
RECOVERY
CH0
VSYNC
HSYNC
DE0
CLT1
CLT2
CLT3
RXC+
VCR
RXC-
PLL
Absolute Maximum Conditions
Note: Permanent device damage may occur if absolute maximum conditions are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage 3.3V
-0.3
4.0
V
V
I
Input Voltage
-0.3
V
CC
+ 0.3
V
V
O
Output Voltage
-0.3
V
CC
+ 0.3
V
T
A
Ambient Temperature (with power applied)
-25
105
°C
T
STG
Storage Temperature
-65
150
°C
Thermal Resistance (Junction to Ambient)
45
°C
/W
θ
JA
Normal Operating Conditions
Symbol
V
CC
V
CCN
T
A
Parameter
Supply Voltage
Supply Voltage Noise
Ambient Temperature (with power applied)
Min
3.0
0
Typ
3.3
25
Max
3.6
100
70
Units
V
mV
P-P
°C
DC Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
High-level Input Voltage
2
V
V
IL
Low-level Input Voltage
0.8
V
V
OH
High-level Output Voltage
2.4
V
V
OL
Low-level Output Voltage
0.4
V
V
CINL
Input Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
1
V
CIPL
Input Clamp Voltage
I
CL
= 18mA
IVCC + 0.8
V
V
CONL
Output Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
V
COPL
Output Clamp Voltage
1
I
CL
= 18mA
OVCC + 0.8
V
I
IL
Input Leakage Current
-10
10
µA
Note:
1
Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions
for a pulse of greater than 3 ns or one third of the clock cycle.
Silicon Image, Inc.
2
Subject to Change without Notice
SiI 141B
DC Specifications
SiI-DS-0037-C
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
OHD
Output High Drive
V
OUT
= 2.4
Data and Controls
ST=1
5.0
10.3
17.6
mA
ST=0
2.5
5.2
8.8
I
OLD
Output Low Drive
V
OUT
= 0.4
Data and Controls
ST=1
-5.5
-8.3
-11.2
mA
ST=0
-2.8
-4.2
-5.6
I
OHC
ODCK High Drive
V
OUT
= 2.4
ST=1
10.1
20.6
35.1
mA
ST=0
5.0
10.3
17.6
I
OLC
ODCK Low Drive
V
OUT
= 2.0
ST=1
-11.1
-16.7
-22.4
mA
ST=0
-5.5
-8.3
-11.2
V
ID
Differential Input Voltage
75
1000
mV
Single Ended Amplitude
I
PDL
Output leakage current to ground in
10
µA
high impedance mode (PD, PDO =
LOW)
I
PD
Power-down Current
1
50
100
µA
I
CLKI
Power-down Current
RXC± Inactive
4
7
mA
I
PDO
Power-down-output Current
125
155
mA
C
LOAD
= 10pF
I
CCR
Receiver Supply Current
ODCK=86MHz, 1-pixel/clock mode
2
157
182
mA
R
EXT_SWING
= 510
Ω
3
Typical Pattern
C
LOAD
= 10pF
172
194
mA
R
EXT_SWING
= 510
Ω
4
Worst Case Pattern
1
Notes:
The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum.
2
For worst case I/O power consumption.
3
The Typical Pattern contains a gray scale area, checkerboard area, and text.
4
Black and white checkerboard pattern, each checker is one pixel wide.
Silicon Image, Inc.
3
Subject to Change without Notice
SiI 141B
AC Specifications
SiI-DS-0037-C
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T
DPS
Intra-Pair (+ to -) Differential Input Skew
86 MHz
470
ps
T
CCS
Channel to Channel Differential Input Skew
86 MHz
7
ns
65 MHz
465
ps
Worst Case Differential Input Clock Jitter tolerance
1,2
T
IJIT
86 MHz
350
ps
D
LHT
Low-to-High Transition Time: Data and Controls
C
L
= 10pF; ST = 1
3.5
ns
(43 MHz, 2-pixel/clock, PIXS=1)
4.5
ns
C
L
= 5pF; ST = 0
Low-to-High Transition Time: Data and Controls
C
L
= 10pF; ST = 1
3.5
ns
(65 MHz, 1-pixel/clock, PIXS=0)
4.5
ns
C
L
= 5pF; ST = 0
Low-to-High Transition Time: ODCK
C
L
= 10pF; ST = 1
1.6
ns
(43 MHz, 2-pixel/clock, PIXS=1)
2.1
ns
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
1.6
ns
Low-to-High Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
C
L
= 5pF; ST = 0
2.1
ns
D
HLT
C
L
= 10pF; ST = 1
3.0
ns
High-to-Low Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
4.2
ns
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
3.0
ns
High-to-Low Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
4.2
ns
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
1.5
ns
High-to-Low Transition Time: ODCK
(43 MHz, 1-pixel/clock, PIXS=0)
1.9
ns
C
L
= 5pF; ST = 0
C
L
= 10pF; ST = 1
1.5
ns
High-to-Low Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
1.9
ns
C
L
= 5pF; ST = 0
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to
T
SETUP
C
L
= 10pF; ST = 1
3.6
ODCK falling edge (OCK_INV = 0) or to ODCK rising
3.0*
ns
edge (OCK_INV = 1)
18.4
ns
C
L
= 5pF; ST = 0
*OCK_INV = 1
19.0*
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from C
L
= 10pF; ST = 1
T
HOLD
8.0
ns
ODCK falling edge, (OCK_INV = 0) or from ODCK rising
8.4*
edge (OCK_INV = 1)
24.0
ns
C
L
= 5pF; ST = 0
*OCK_INV = 0
24.5*
R
CIP
ODCK Cycle Time (1 pixel/clock)
11.6
40
ns
F
CIP
ODCK Frequency (1 pixel/clock)
25
86
MHz
R
CIP
ODCK Cycle Time (2 pixels/clock)
23.3
80
ns
F
CIP
ODCK Frequency (2 pixels/clock)
12.5
43
MHz
C
L
= 10pF, ST=1
5.0
R
CIH
ODCK High Time
4.4
ns
65 MHz, One Pixel / Clock, PIXS = 0
3
C
L
= 5pF, ST=0
9.0
ns
43 MHz, Two Pixel / Clock, PIXS = 1
3
C
L
= 10pF, ST=1
8.2
C
L
= 5pF, ST=0
C
L
= 10pF, ST=1
6
R
CIL
ODCK Low Time
5
ns
65 MHz, One Pixel / Clock, PIXS = 0
3
C
L
= 5pF, ST=0
9
ns
43 MHz, Two Pixel / Clock, PIXS = 1
3
C
L
= 10pF, ST=1
9
C
L
= 5pF, ST=0
T
HSC
Link disabled (DE inactive) to SCDT low
1
160
ms
5
Link disabled (Tx power down) to SCDT low
200
250
ms
T
FSC
Link enabled (DE active) to SCDT high
6
Falling
40
DE edges
T
CLKPD
Delay from RXC+/- Inactive to high impedance outputs
RXC+/- = 25MHz
10
µs
T
CLKPU
Delay from RXC+/- active to data active
RXC+/- = 25MHz
100
µs
T
PDL
Delay from PD/ PDO Low to high impedance outputs
8
ns
1
Notes:
Jitter defined as per DVI 1.0 Specification, Section 4.6
Jitter Specification.
2
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7
Electrical Measurement Procedures.
3
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
4
The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same
as the falling edge timing.
5
Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design /Application Guide,” Section 2.4).
6
Refer to the transmitter datasheet for minimum DE high and low time
7
Data is active (i.e. not tri-stated) but not valid yet. Data and controls are valid only when SCDT goes high. See T
FSC
and
Figure 7.
Silicon Image, Inc.
4
Subject to Change without Notice
SiI 141B
Timing Diagrams
SiI-DS-0037-C
2.0 V
SiI141B
10pF (5pF)
0.8 V
D
LHT
2.0 V
0.8 V
D
HLT
Figure 1. Digital Output Transition Times
R
CIP
R
CIH
2.0 V
2.0 V
2.0 V
0.8 V
R
CIL
Figure 2. Receiver Clock Cycle/High/Low Times
0.8 V
RX0
V
DIFF
= 0V
RX1
T
CCS
V
DIFF
= 0V
RX2
Figure 3. Channel-to-Channel Skew Timing
Output Timing
ODCK_INV = 1
ODCK_INV = 0
T
SETUP
T
HOLD
QE[23:0]/QO[23:0],
DE, VSYNC, HSYNC,
CTL[3:1]
Figure 4. Output Data Setup/Hold Times to ODCK
Silicon Image, Inc.
5
Subject to Change without Notice
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