IRFBE30S, SiHFBE30S, IRFBE30L, SiHFBE30L
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
()
Q
g
(Max.) (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
78
9.6
45
Single
D
FEATURES
800
3.0
•
Halogen-free According to IEC 61249-2-21
Definition
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Fast Switching
• Ease of Paralleling
• Simple Drive Requirements
• Compliant to RoHS Directive 2002/95/EC
I
2
PAK
(TO-262)
D
2
PAK
(TO-263)
DESCRIPTION
G
G
D
G
S
D
S
S
N-Channel MOSFET
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D
2
PAK (TO-263)
SiHFBE30S-GE3
IRFBE30SPbF
SiHFBE30S-E3
D
2
PAK (TO-263)
SiHFBE30STRL-GE3
a
IRFBE30STRLPbF
a
SiHFBE30STL-E3
a
I
2
PAK (TO-262)
SiHFBE30L-GE3
IRFBE30LPbF
SiHFBE30L-E3
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
a
Linear Derating Factor
Single Pulse Avalanche
Avalanche Current
a
Repetitive Avalanche Energy
a
Maximum Power Dissipation
Peak Diode Recovery
dV/dt
c
for 10 s
6-32 or M3 screw
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
T
C
= 25 °C
Energy
b
E
AS
I
AR
E
AR
P
D
dV/dt
T
J
, T
stg
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
LIMIT
800
± 20
4.1
2.6
16
1.0
260
4.1
13
125
2.0
- 55 to + 150
300
d
10
1.1
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
A
UNIT
V
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 29 mH, R
g
= 25
,
I
AS
= 4.1 A (see fig. 12).
c. I
SD
4.1 A, dI/dt
100 A/μs, V
DD
600 V, T
J
150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91119
S11-1053-Rev. C, 30-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFBE30S, SiHFBE30S, IRFBE30L, SiHFBE30L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
SYMBOL
R
thJA
R
thCS
R
thJC
MIN.
-
-
-
TYP.
-
0.50
-
MAX.
62
-
1.0
°C/W
UNIT
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
Current
a
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
DS
= 800 V, V
GS
= 0 V
V
DS
= 640 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 2.5 A
b
V
DS
= 100 V, I
D
= 2.5 A
800
-
2.0
-
-
-
-
2.5
-
0.90
-
-
-
-
-
-
-
-
4.0
± 100
100
500
3.0
-
V
V/°C
V
nA
μA
S
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
-
-
-
-
1300
310
190
-
-
-
12
33
82
30
4.5
7.5
-
-
-
78
9.6
45
-
-
-
-
-
nH
-
ns
nC
pF
V
GS
= 10 V
I
D
= 4.1 A, V
DS
= 400 V,
see fig. 6 and 13
b
-
-
-
V
DD
= 400 V, I
D
= 4.1 A,
R
g
= 12
,
R
D
= 95
,
see fig. 10
b
-
-
-
Between lead,
6 mm (0.25") from
package and center of
die contact
D
-
-
G
S
-
-
-
-
-
-
-
-
480
1.8
4.1
A
16
1.8
720
2.7
V
ns
nC
G
S
T
J
= 25 °C, I
S
= 4.1 A, V
GS
= 0 V
b
T
J
= 25 °C, I
F
= 4.1 A, dI/dt = 100 A/μs
b
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width
300 μs; duty cycle
2 %.
www.vishay.com
2
Document Number: 91119
S11-1053-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFBE30S, SiHFBE30S, IRFBE30L, SiHFBE30L
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, T
C
= 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, T
C
= 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91119
S11-1053-Rev. C, 30-May-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFBE30S, SiHFBE30S, IRFBE30L, SiHFBE30L
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
www.vishay.com
4
Document Number: 91119
S11-1053-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFBE30S, SiHFBE30S, IRFBE30L, SiHFBE30L
Vishay Siliconix
V
DS
V
GS
R
g
R
D
D.U.T.
+
- V
DD
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
Fig. 9 - Maximum Drain Current vs. Case Temperature
t
d(on)
t
r
t
d(off)
t
f
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary t
p
to obtain
required I
AS
R
g
V
DS
t
p
V
DD
D.U.T.
I
AS
10 V
t
p
0.01
Ω
I
AS
Fig. 12b - Unclamped Inductive Waveforms
V
DS
+
-
V
DD
V
DS
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91119
S11-1053-Rev. C, 30-May-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
