IRF9Z24S, SiHF9Z24S
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
()
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= - 10 V
19
5.4
11
Single
- 60
0.28
•
•
•
•
•
•
•
Advanced process technology
Surface mount (IRF9Z24S, SiHF9Z24S)
175 °C operating temperature
Available
Fast switching
P-channel
Available
Fully avalanche rated
Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
S
D
2
PAK (TO-263)
DESCRIPTION
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D
2
PAK is a surface mount power package capable of
accommodating die size up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D
2
PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0 W in a typical surface mount application.
G
G D
S
D
P-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D
2
PAK (TO-263)
SiHF9Z24S-GE3
IRF9Z24SPbF
D
2
PAK (TO-263)
SiHF9Z24STRL-GE3
a
IRF9Z24STRLPbF
a
D
2
PAK (TO-263)
SiHF9Z24STRR-GE3
a
IRF9Z24STRRPbF
a
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
e
Pulsed Drain Current
a, e
Linear Derating Factor
Single Pulse Avalanche Energy
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
Maximum Power Dissipation
Peak Diode Recovery dV/dt
c, e
a
b, e
SYMBOL
V
DS
V
GS
V
GS
at -10 V
T
C
= 25 °C
T
C
= 100 °C
I
D
I
DM
E
AS
I
AR
E
AR
T
A
= 25 °C
T
C
= 25 °C
P
D
dV/dt
T
J
, T
stg
for 10 s
LIMIT
-60
± 20
-11
-7.7
-44
0.40
240
-11
6.0
3.7
60
-4.5
-55 to +175
300
UNIT
V
A
W/°C
mJ
A
mJ
W
W
V/ns
°C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature)
d
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= - 25 V, starting T
J
= 25 °C, L = 2.3 mH, R
g
= 25
,
I
AS
= - 11 A (see fig. 12).
c. I
SD
- 11 A, dI/dt
140 A/μs, V
DD
V
DS
, T
J
175 °C.
d. 1.6 mm from case.
e. Uses IRF9Z24, SiHF9Z24 data and test conditions.
S16-0015-Rev. D, 18-Jan-16
Document Number: 91091
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF9Z24S, SiHF9Z24S
www.vishay.com
Vishay Siliconix
SYMBOL
R
thJA
R
thJC
MIN.
-
-
TYP.
-
-
MAX.
40
2.5
UNIT
°C/W
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
(PCB mount)
a
Maximum Junction-to-Case (Drain)
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
a
Body Diode Voltage
Drain-Source Body Diode Characteristics
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
t
rr
Q
rr
t
on
T
J
= 25 °C, I
F
= -11 A, dI/dt = 100 A/μs
b, c
-
-
100
320
200
640
ns
nC
I
S
I
SM
V
SD
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
TEST CONDITIONS
V
GS
= 0, I
D
= -250 μA
Reference to 25 °C, I
D
= -1 mA
c
V
DS
= V
GS
, I
D
= -250 μA
V
GS
= ± 20 V
V
DS
= -60 V, V
GS
= 0 V
V
DS
= -48 V, V
GS
= 0 V, T
J
= 150 °C
V
GS
= -10 V
I
D
= -6.6 A
b
V
DS
= -25 V, I
D
= -6.6 A
c
MIN.
-60
-
-2.0
-
-
-
-
1.4
-
-
-
-
-
-
-
TYP.
-
-0.056
-
-
-
-
-
-
570
360
65
-
-
-
13
68
15
29
-
-
-
MAX.
-
-
-4.0
± 100
-100
-500
0.28
-
-
-
-
19
5.4
11
-
-
-
-
-11
-44
-6.3
UNIT
V
V/°C
V
nA
μA
S
V
GS
= 0 V,
V
DS
= - 25 V,
f = 1.0 MHz, see fig. 5
c
I
D
= -11 A, V
DS
= -48 V,
see fig. 6 and 13
b, c
pF
V
GS
= -10 V
nC
V
DD
= -30 V, I
D
= -11 A,
R
g
= 18
,
R
D
= 2.5
,
see fig. 10
b
-
-
-
-
-
ns
G
A
S
T
J
= 25 °C, I
S
= -11 A, V
GS
= 0 V
b
-
V
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width
300 μs; duty cycle
2 %.
c. Uses IRF9Z24, SiHF9Z24 data and test conditions.
S16-0015-Rev. D, 18-Jan-16
Document Number: 91091
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF9Z24S, SiHF9Z24S
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
V
GS
Top
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
Vishay Siliconix
3.0
2.5
2.0
1.5
1.0
0.5
I
D
= - 11 A
V
GS
= - 10 V
- I
D
, Drain Current (A)
10
1
10
0
- 4.5 V
20 µs Pulse Width
T
C
=
25 °C
10
-1
91091_01
10
0
10
1
0.0
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 180
- V
DS
, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
91091_04
T
J,
Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
- I
D
, Drain Current (A)
Capacitance (pF)
10
1
V
GS
Top
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
- 4.5 V
1250
1000
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
Shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
750
C
iss
500
C
oss
10
0
250
20 µs Pulse Width
T
C
=
175 °C
10
-1
10
0
10
1
91091_05
C
rss
0
10
0
10
1
91091_02
- V
DS,
Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
- V
DS,
Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
- V
GS
, Gate-to-Source Voltage (V)
I
D
= - 11 A
V
DS
= - 48 V
- I
D
, Drain Current (A)
10
1
25
°
C
175
°
C
16
V
DS
= - 30 V
12
10
0
8
4
For test circuit
see figure 13
20 µs Pulse Width
V
DS
= -
25 V
4
91091_03
0
0
91091_06
5
6
7
8
9
10
5
10
15
20
25
- V
GS,
Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Q
G
, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S16-0015-Rev. D, 18-Jan-16
Document Number: 91091
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF9Z24S, SiHF9Z24S
www.vishay.com
Vishay Siliconix
15
- I
SD
, Reverse Drain Current (A)
175
°
C
25
°
C
- I
D
, Drain Current (A)
10
1
12
9
10
0
6
3
10
-1
0.5
91091_07
V
GS
= 0 V
1.5
2.5
3.5
4.5
5.5
91091_09
0
25
50
75
100
125
150
175
- V
SD
, Source-to-Drain Voltage (V)
T
C
, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
R
D
V
DS
V
GS
D.U.T.
+
-
- 10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
10
2
5
R
g
Operation in this area limited by R
DS(on)
10
µs
100
µs
1
ms
V
DD
- I
D
, Drain Current (A)
2
10
5
Fig. 10a - Switching Time Test Circuit
2
10
ms
t
d(on)
V
GS
T
C
= 25
°C
T
J
= 175
°C
Single Pulse
0.1
2
5
1
5
t
r
t
d(off)
t
f
10 %
2
0.1
1
2
5
10
2
5
10
2
2
5
10
3
90 %
V
DS
91091_08
- V
DS
, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Fig. 10b - Switching Time Waveforms
10
Thermal Response (Z
thJC
)
1
D = 0.50
0.2
0.1
P
DM
t
1
t
2
Notes:
1. Duty Factor, D = t
1
/t
2
2. Peak T
j
= P
DM
x Z
thJC
+ T
C
10
-5
10
-4
10
-3
10
-2
0.1
1
10
0.1
0.05
0.02
0.01
Single Pulse
(Thermal Response)
10
-2
91091_11
t
1
, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S16-0015-Rev. D, 18-Jan-16
Document Number: 91091
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF9Z24S, SiHF9Z24S
www.vishay.com
Vishay Siliconix
L
Vary t
p
to obtain
required I
AS
R
g
V
DS
I
AS
D.U.T.
I
AS
V
DS
-
+ V
DD
V
DD
t
p
- 10 V
t
p
0.01
Ω
V
DS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
800
E
AS
, Single Pulse Energy (mJ)
600
I
D
- 4.5 A
- 7.8 A
Bottom - 11 A
Top
400
200
0
V
DD
= - 25 V
25
50
75
100
125
150
175
91091_12c
Starting T
J
, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
12 V
- 10 V
Q
GS
Q
G
0.2 µF
0.3 µF
V
G
V
GS
- 3 mA
Charge
I
G
I
D
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
S16-0015-Rev. D, 18-Jan-16
Document Number: 91091
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
+
D.U.T.
-
Q
GD
V
DS
FPGA/CPLD
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