AN727
Vishay Siliconix
High-Frequency, High-Efficiency Buck Converter Design For
Multi-Cell Battery Configured Systems Using Si9167
Nitin Kalje
INTRODUCTION
The Si9167 is a high-frequency synchronous dc-to-dc
switching buck regulator, with an operating range suitable for
two-cell Li+ battery-powered applications. Capable of
operation up to 2 MHz, the Si9167 can be used to supply
power amplifiers and to power up baseband circuits in satellite
phones. Its high operating frequency reduces the size of
inductor and capacitor components, while its low
on-resistance internal driver ensures maximum power
conversion efficiency. Additional features include an
integrated input undervoltage lockout, power on reset,
integrated soft start, light load pulse skipping mode selection,
synchronization, clock output for master-slave configuration of
multiple regulators, uncommitted power-good comparator,
and over temperature protection. An output power in excess of
2 W at 3.6 V
O
is possible in 0.3 square inches.
TYPICAL APPLICATION CIRCUIT
+V
IN
5 - 10 V
1
C1
10
mF
16 V
PGND
2
R1*
51
W
C1
0.1
mF
Si9167
ENABLE/DISABLE
PWM/PSM
R9*
51 kW
1
2
3
4
5
6
7
8
1.3 V
C3
0.1
mF
9
10
SD
PWM/PSM
V
IN
V
IN
POK
SYNC
CLK
GND
V
REF
FB
COIL
COIL
PGND
COIL
PGND
POKIN
V
O
V
DD
R
OSC
COMP
R3
8.2 kW
C5
1000 pF
C4
56 pF
20
MBRO520T1
19
18
17
16
15
14
13
12
11
R2
75 kW
D1
3.6 V @ 600 mA
L1
4.7
mH
IHLP2525
C1
10
mF
16 V
C9
0.1
mF
7
V
OUT
8
PGND
R7
105 kW
R8
64 kW
C6
0.1
mF
R4
200
W
C7
330 pF
R6
12.4 kW
R5
22 kW
STAR GND CON
* Optional
FIGURE 1.
Typical Application Circuit—Buck
Document Number: 70959
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FUNCTIONAL BLOCK DIAGRAM
V
DD
Positive Supply
SD
V
IN
Reference
Threshold
Generator
V
REF
V
O
FB
COMP
1.3 V
Soft-Start
Timer
UVLO
POR
System Monitor
Bias
Generator
OTP
PWM
Modulator
1.0 V
Ramp
Oscillator
C
OSC
PWM
IN
0.5 V
PWM
IN
PWM/PFM
Select
PSM
IN
PSM
IN
PSM
Modulator
–
+
Drivers
COIL
SYNC
CLK
R
OSC
POKIN
POK
PWM/PSM
Negative Return
and
Substrate
GND
PGND
FIGURE 2.
DESIGN GUIDELINES
The following section describes key device features and
provides general guidelines for designing a buck regulator with
the Si9167.
Voltage Mode Control
For cellular phone and PDA applications, voltage-mode
control provides a number of advantages, including the
avoidance of power dissipation in current sensing elements,
greater noise immunity (since the PWM signal can be as high
as 1 V), and a less complicated single feedback loop to
compensate with.
The BiCMOS process used in the Si9167 improves
voltage-mode performance by increasing the operating
frequency and thereby pushing the closed loop bandwidth to
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+
–
1.0 V
0.5 V
more than 100 kHz. Since the intended applications for this
device involves a battery input, such that rapid changes in
voltage level are not involved, there is no need for a fast input
dynamic response as offered by current mode control.
Oscillator
FIGURE 3.
Voltage Mode Control
2
Document Number: 70959
07-Jul-99
AN727
Vishay Siliconix
In the Si9167, the error amplifier output is compared with the
0.5-V peak-to-peak sawtooth waveform elevated by a 0.5-V
offset (Figure 3). The offset provides sufficient noise immunity,
even at 2-MHz switching frequencies and 1V/nSec MOSFET
switching. The error amplifier has an open loop gain of 60 dB
with a 2-MHz unity gain bandwidth. This feature helps to
simplify compensation and further increase the closed loop
bandwidth. The only external component required to set the
oscillator frequency is a resistor at R
osc
(pin12). The oscillator
generates a
"20%
tolerance frequency with a
"1%
resistor.
High Frequency Operation
Low power dc-to-dc regulator designers must consider both
the on-resistance of the switches and the gate charge required
to turn them on and off. Conventional MOSFETs need more
gate charge per ampere of current rating, while Vishay
Siliconix’s extremely low gate charge, PWM optimized
MOSFET technology offers optimum performance even
above 1-MHz switching frequencies. The Si9167 has 180-mW
internal drivers and requires a very low gate charge drive,
translating into lower switching losses at higher frequencies.
Moreover, lower gate charge helps increase the switching
speed for a given drive power. This further improves efficiency
by reducing crossover losses. For this reason, the Si9167 can
achieve up to 93% efficiency even when operating at 1 MHz.
Efficiency curves for a 3.6-V buck regulator at various input
voltage levels are provided in Figure 4.
hysteresis losses in an inductor, as well as ESR losses in
capacitors, are the limiting factors in going to higher operating
frequencies. Moreover, the effective impedance of capacitors
and inductors at higher operating frequencies are dominated
by ESL, ESR, and interlayer capacitance, which causes
inductors to behave more like capacitors and capacitors to
behave more like inductors.
The low-profile, high-current IHLP inductor series from
Vishay Dale offers excellent high-frequency performance, as
do very low-ESR, high-capacity multilayer ceramic capacitors,
such that output ripple is inversely proportional to the switching
frequency and not determined by the ESR. The X5R series
from Murata and the Y5U series from Tokin are recommended
dielectrics.
Practical Inductor
Rdc
Rdc
Rac
Cp
L
C
p
L
= dc Resistance of Copper
= Skin Effect Related ac resistance
= Interlayer Capacitance
Ideal Inductance
Rac
Efficiency, V
O
= 3.6 V
100
PWM–V
IN
= 7.2 V
90
PSM–V
IN
= 5 V
PSM–V
IN
= 7.2 V
Efficiency (%)
80
PWM–V
IN
= 5 V
PWM–V
IN
= 8.4 V
Practical Capacitor
70
PSM–V
IN
= 8.4 V
R
ESR
R
ESR
Rp
C
R
ESL
= Equivalent Series Resistance
= Insulation Resistance
= Interlayer Capacitance
Equivalent Series Inductance
60
R
ESL
50
10
100
Load Current (mA)
1000
C
R
p
FIGURE 4.
Efficiency vs. Output Load
Passive Components
Within limits, high switching frequencies reduce the size of
passive components. Frequency-dependent skin effect and
Document Number: 70959
07-Jul-99
FIGURE 5.
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V
IN
= 7.2 V, V
O
= 3.6 V, I
O
= 150 mA
Ch1: V
OUT
(200 mV/div)
Ch2: Inductor Current (500 mA/div)
Ch3: PWM/PSM (High PWM, Low PSM)
FIGURE 6.
PSM-PWM-PSM Transition
PSM-PWM Operation
The Si9167 can operate in either fixed-frequency PWM mode
or fixed on-time pulse skipping mode (PSM). Switching losses
resulting from the gate charge of the driver and internal
BICMOS circuitry are fixed irrespective of the output power
drawn from the converter. At lower output levels, the
percentage of these losses is high, which makes the circuit
less efficient. Therefore, at output loads lower than 150 mA,
PSM operation is recommended. PSM operation reduces the
operating frequency, depending upon the load, which in turn
reduces the switching losses proportionally and keeps the
efficiency high at all load current levels.
output capacitance and ESR. The capacitor must be selected
for an acceptable droop in output voltage at a maximum load
current in PSM, and is given by the following equation:
V
O_DROP
+
I
OUT
t
BLANK
)
ESR
C
OUT
(1)
Where
V
O_DROP
t
BLANK
C
OUT
ESR
I
OUT
=
=
=
=
=
Output droop during Transition (V)
Blanking time (S)
Output Capacitor (F)
ESR of output Capacitor (W)
Output Load (A)
Inductor Selection
Low operating frequencies can become a concern if they are
in the audible range. Special care has been taken in the Si9167
to ensure that the operating frequency will always be above
20 kHz in pulse-skipping mode at output load currents as low
as 6 mA. A load current of 150 mA is guaranteed in PSM, while
PWM mode is used for higher load current operation. In this
way, converter efficiency is always optimized. Efficiency
versus load plots are provided in figures 14 and 15.
A wide selection of inductors is available from vendors such as
Vishay Dale, Coiltronix, and Sumida. Major factors to consider
include inductance value, saturating current, and equivalent
series resistance (RL).
Since the Si9167 can be operated at up to 2 MHz, required
inductance for a given output capacitor and ripple current
could be as low as 1.5
mH,
where:
Two different sections control the operation of the converter in
either PWM mode or PSM. When PWM mode is selected, the
PWM control section is active, thereby disabling the PSM
control and vice versa. During the PWM-to-PSM transition,
there is an overlapping time between the PWM and the PSM
circuit activation, which keeps the output voltage from
drooping. However, while transitioning from PSM to PWM,
there is no such overlap. The time needed to activate the PWM
circuit, after the PSM circuit is turned off, is called the blanking
time. During this time there are no pulses. This blanking time
is typically between 5 to 10
ms.
Figure 6 shows the behavior of
the output voltage, output, and coil current during the PSM-
PWM-PSM transition. The sag in the output depends upon the
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MIN
+
dMIN
+
V
INMAX
*
V
DSQP
*
V
OUT
)
V
R_DROP
dMIN
0.72
V
OUT
)
V
R_DROP
V
INMAX
*
V
DSQP
I
OUT
I
OUT
Fsw
DI
(2)
V
DSQP
+
0.42
V
R_DROP
+
R
L
)
R
TRACE
4
Document Number: 70959
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AN727
Vishay Siliconix
Where
V
INMAX
= Maximum input voltage (V)
V
OUT
= Output Voltage (V)
V
DSQP
= Voltage drop across the main switch (V)
DI
= Max ripple current allowed for acceptable ripple (A)
dMIN=
Duty ratio at V
INMAX
.
V
R_DROP
= Resistive drop through inductor and PCB traces (V)
I
OUT
= Rated output current (A)
R
L
= Equivalent Series Resistance (W)
R
TRACE
= Combined resistance of positive and negative output
traces (W)
Fsw = Oscillator Frequency (Hz)
R6
+
V
R5
OUT
(3)
V REF
*
1
The typical value for V
REF is 1.3 V.
Power_Good Comparator
The inverting input is internally connected to the reference
voltage of 1.3 V (see functional block diagram, Figure 2). This
uncommitted comparator, with about 50 mV hysteresis, is
intended to be used to sense the output voltage and raise a
high flag once the output voltage Vout reaches its regulation
limit. The 50-mV hysteresis at the comparator input is provided
while output is transitional from high to low. The output is
capable of sourcing 2
mA
and sinking 1 mA current. The source
current can be increased up to 1 mA by pulling the output high
with an external resistor (Figure 1). Use following equation for
the POK to switch to high at a V
OL
and to low at
[V
OL
– V
HYSTERESIS
].
Refer to Figure 7 when deciding the inductance and frequency.
The frequency V
S
inductance plot assumes a 10-mF ceramic
multilayer chip capacitor with a 20-mW maximum ESR and
10-mVp-p output ripple.
F
SW
vs. Inductance
16
14
12
10
L (
m
H)
8
6
V
IN
POK (V)
4
2
0
300
V
OL
+
1.3
(R7
)
R8)
Volts
R8
(R7
)
R8)
mVolts
R8
(4)
V
HYSTERESIS
+
50
500
700
900
1100 1300 1500 1700 1900
(V
OL
– V
HYSTERESIS
)
(V
OL
)
F
sw
(kHz)
FIGURE 7.
Inductor Value Selection for 10-mF Ceramic
Output Capacitor
FIGURE 8.
V
OUT
(V)
Synchronization
Output Voltage
Systems using more than one converter for power
management functions often face EMC problems. The
reflected ripple at the inputs from these independent
converters, which operate at different frequencies and phases,
can create a wide frequency range of harmonics. Obviously, it
is difficult, if not impossible, to eliminate all of these from the
emission spectrum. The alternatives are to incorporate a
heavy filter at the input of each converter or let all converters
oscillate at the same frequency and phase.
The divider resistor pair, R5 and R6 in Figure 1 determine the
output regulation point. Since R5 is part of the compensation
network, it is strongly recommended that R6 be adjusted in
order to change the regulation voltage without affecting the
loop gain. With fixed R5, R6 can be easily calculated by (3) for
the desired output voltage setting.
Document Number: 70959
07-Jul-99
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