a. Device mounted with all leads soldered or welded to PC board.
b. Derate 9.52 mW/_C above 70_C.
New Product
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Test Conditions
Parameter
Buck Controller A
Total Regulation (Line, Load, and Temperature)
Line Regulation
Load Regulation
Current Limit
Bandwidth
Phase Margin
Minimum Duty Cycle
V
IN
= 4.5 V to 30 V, 0 < V
CS3
- V
FB3
< 90 mV
V
IN
= 6.0 V to 30 V
V
IN
= 4.5 V to 30 V
0 < V
CS3
- V
FB3
< 90 mV
V
CSA
- V
FBA
L = 10
mH,
C = 330
mF
R
SENSE
= 20 mW
V
OUT
>
2.5 V
V
OUT
<
2.5 V
90
100
50
65
7
125
-3
0
3
±0.5
±1.0
±0.5
160
180
mV
kHz
_
%
%
V
IN
= 15 V , I
VL
= I
REF
= 0 mA
T
A
= -40_C to 85_C, All Controllers ON
Limits
Min
a
Typ
b
Max
a
Unit
Buck Controller B
Total Regulation (Line, Load, and Temperature)
Line Regulation
Load Regulation
Current Limit
Bandwidth
Phase Margin
Minimum Duty Cycle
V
IN
= 4.5 V to 30 V, 0 < V
CS5
- V
FB5
< 90 mV
V
IN
= 6.0 V to 30 V
V
IN
= 4.5 V to 30 V
0 < V
CSB
- V
FBB
< 90 mV
V
CSB
- V
FBB
L = 10
mH,
C = 330
mF
R
SENSE
= 20 mW
V
OUT
>
2.5 V
V
OUT
<
2.5 V
90
100
50
65
7
125
-3
0
3
±0.5
±1.0
±0.5
160
180
mV
kHz
_
%
%
Auxiliary Controller C
Total Regulation (Line, Load, and Temperature)
Output Voltage Set to 12 V
Line Regulation
Load Regulation
Current Limit
Bandwidth
Phase Margin
Current-Sense Common Mode Voltage Range
Feedback Input Voltage Range
Minimum Duty Cycle
Maximum Duty Cycle
V
IN
= 5 V
V
IN
= 4.5 V to 30 V, 0 < V
CSP
- V
CSN
< 300 mV
R
5
= 26.4 kW, R
6
= 10 kW (See Figure 1)
V
IN
= 6.0 V to 30 V
V
IN
= 4.5 V to 30 V
0 < V
CSP
- V
FBN
< 300 mV
V
CSP
- V
CSN
L = 10
mH,
C = 100
mF
R
SENSE
= 100 mW, C
comp
= 120 pF
0.0
0.0
7
85
%
280
360
10
65
2.1
2.1
V
-5
0
5
±0.5
±1.0
±0.5
450
mV
kHz
_
%
www.vishay.com
2
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
Si9139
New Product
SPECIFICATIONS
Test Conditions
Parameter
Internal 5-V Regulator
V
L
Output Current (Internal and External)
V
L
Output
V
L
Fault Lockout Voltage
V
L
Fault Lockout Hysteresis
All Controllers OFF, V
IN
>5.5 V, 0 <I
L
<30 mA
V
L
Falling Edge
4.7
3.6
75
30
60
5.5
4.2
V
mV
mA
V
IN
= 15 V , I
VL
= I
REF
= 0 mA
T
A
= -40_C to 85_C, All Controllers ON
Vishay Siliconix
Limits
Min
a
Typ
b
Max
a
Unit
Reference
REF Output
REF Load Regulation
Auxiliary Feedback Voltage
FB
C
Pin
0 to 1 mA
1.20
3.24
3.3
25
1.24
3.36
60
1.28
V
mV
V
Supply Current
Supply Current*Shutdown
Supply Current*Operation
All Converters OFF, No Load
All Controllers ON, No Load, f
OSC
= 300 kHz
25
1100
60
1800
mA
m
Oscillator
Oscillator Frequency
Maximum Duty Cycle
270
92
300
95
330
kHz
%
Fault Detection SMPS
A
and SMPS
B
Outputs
Overvoltage Trip Threshold
Overvoltage-Fault Propagation Delay
Output Undervoltage Threshold
Output Undervoltage Lockout Time
With Respect To Unloaded Output Voltage
CS
A
or CS
B
Driven 2% Above Overvoltage Trip
Threshold
With Respect to Unloaded Output Voltage
From each SMPS Enabled
-40
16
6
10
1.5
-30
20
-20
24
14
%
ms
%
ms
RESET
RESET Start Threshold
RESET Propagation Delay (Falling)
RESET Delay Time (Rising)
With Respect To Unloaded Output Voltage
Rising Edge
Falling Edge, FB
A
or FB
B
Driven 2% Above Overvol-
tage or 2% Below Undervoltage Lockout Thresholds
With Respect to 2nd SMPS Lockout Time Done
92
-5.5
1.5
107
122
%
ms
ms
Inputs and Outputs
Feedback Input Leakage Current
Input Leakage Current
Gate Driver Sink/Source Current (Buck)
Gate Driver On-Resistance (Buck)
Gate Driver Sink/Source Current (Auxiliary)
Gate Driver On-Resistance (Auxiliary)
RESET Output Low Voltage
RESET Output High Leakage
FB
C
= 1.24 V
ON
A
, ON
B
, V
IN
= 0 V or V
L
DL
A
, DH
A
, DL
B
, DH
B
Forced to 2 V
High or Low
DH
C
, DL
C
Forced to 2 V
High or Low
RESET, I
SINK
= 4 mA
RESET = 5 V
1
2
0.2
15
0.4
1
7
1
"1
mA
m
A
W
A
W
V
mA
ON
A
, ON
B
Logic Low
Logic High
V
IL
V
IH
2.4
0.8
V
Notes
a. The algebraic convention is used whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing, and are measured at T
A
= 25_C.
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
3
Si9139
Vishay Siliconix
PIN CONFIGURATION
New Product
RESET
FB
C
BST
C
DH
C
LX
C
DL
C
CSP
CSN
COMP
GND
REF
ON
A
ON
B
CS
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP-28
Top View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CS
A
FB
A
DH
A
LX
A
BST
A
DL
A
V
IN
V
L
FB
B
PGND
DL
B
BST
B
LX
B
DH
B
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
RESET
FB
C
BST
C
DH
C
LX
C
DL
C
CSP
CSN
COMP
GND
REF
ON
A
ON
B
CS
B
DH
B
LX
B
BST
B
DL
B
PGND
FB
B
V
L
V
IN
DL
A
BST
A
LX
A
DH
A
FB
A
CS
A
Description
Open drain NMOS output active-low timed reset output. RESET swings GND to V
L
. Goes high after a fixed 32,000 clock
cycle delay following proper power-up of all supply outputs indicating Power_Good.
Feedback for Auxiliary controller C. Normally connected to an external resistor divider used to set the Auxiliary output
voltage.
Boost capacitor connection for Auxiliary SMPS controller C
Gate-drive output for Auxiliary SMPS controller C high-side MOSFET
Inductor connection for Auxiliary SMPS controller C
Gate-drive output for Auxiliary SMPS controller C low-side MOSFET
Current sense positive input for Auxiliary SMPS controller C
Current sense negative input for Auxiliary SMPS controller C
Auxiliary SMPS controller C compensation connection, if required
Analog ground
3.3-V internal reference
Logic High enables the SMPS controller A
Logic High enables the SMPS controller B and the Auxiliary SMPS controller C adjustable SMPS controllers
Current sense input for SMPS controller B
Gate-drive output for SMPS controller B high-side MOSFET
Inductor connection for SMPS controller B
Boost capacitor connection for SMPS controller B
Gate-drive output for SMPS controller B low-side MOSFET
Power ground
Feedback for SMPS controller B
5-V logic supply voltage for internal circuitry
Input voltage
Gate-drive output for SMPS controller A low-side MOSFET
Boost capacitor connection for SMPS controller A
Gate-drive output for SMPS controller A high-side MOSFET
Inductor connection for SMPS controller A low-side MOSFET
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
