b. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71911
S09-0227-Rev. F, 09-Feb-09
www.vishay.com
1
Si7540DP
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
V
GS(th)
I
GSS
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= 0 V, V
GS
= ± 8 V
V
DS
= 12 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= - 12 V, V
GS
= 0 V
V
DS
= 12 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
= - 12 V, V
GS
= 0 V, T
J
= 55 °C
On-State Drain Current
a
I
D(on)
V
DS
≥
5 V, V
GS
= 4.5 V
V
DS
≤ −
5 V, V
GS
= - 4.5 V
V
GS
= 4.5 V, I
D
= 11.8 A
Drain-Source On-State Resistance
a
R
DS(on)
V
GS
= - 4.5 V, I
D
= - 8.9 A
V
GS
= 2.5 V, I
D
= 9.8 A
V
GS
= - 2.5 V, I
D
= - 6.9 A
Forward Transconductance
a
Diode Forward Voltage
a
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery
Time
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
rr
N-Channel
V
DD
= 6 V, R
L
= 6
Ω
I
D
≅
1 A, V
GEN
= 4.5 V, R
g
= 6
Ω
P-Channel
V
DD
= - 6 V, R
L
= 6
Ω
I
D
≅
- 1 A, V
GEN
= - 4.5 V, R
g
= 6
Ω
I
F
= 2.9 A, dI/dt = 100 A/µs
I
F
= - 2.9 A, dI/dt = 100 A/µs
P-Channel
V
DS
= - 6 V, V
GS
= - 4.5 V, I
D
= - 8.9 A
N-Ch
N-Channel
V
DS
= 6 V, V
GS
= 4.5 V, I
D
= 11.8 A
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
0.5
1.5
11.5
13
3.2
4.1
2.5
1.9
1.7
3.5
30
35
50
42
60
54
25
17
40
40
2.5
5.6
45
55
75
65
90
85
40
30
80
80
ns
Ω
17
20
nC
g
fs
V
SD
V
DS
= 5 V, I
D
= 11.8 A
V
DS
= - 5 V, I
D
= - 8.9 A
I
S
= 2.9 A, V
GS
= 0 V
I
S
= - 2.9 A, V
GS
= 0 V
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
20
- 20
0.014
0.026
0.020
0.043
32
23
0.77
- 0.8
1.2
- 1.2
0.017
0.032
0.025
0.053
S
V
Ω
0.6
- 0.6
1.5
- 1.5
± 100
± 100
1
-1
5
-5
A
µA
V
nA
Symbol
Test Condition
Min.
Typ.
Max.
Unit
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
淘e淘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
