SPICE Device Model Si7401DN
Vishay Siliconix
P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
•
P-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
mode
is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0-to-5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71638
31-May-01
www.vishay.com
1
SPICE Device Model Si7401DN
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
Symbol
Test Condition
Simulated
Data
Measured
Data
Unit
V
GS(th)
I
D(on)
V
DS
= V
GS
, I
D
=
−
2mA
V
DS
=
−
5V, V
GS
=
−
4.5 V
V
GS
=
−
4.5V, I
D
=
−
11A
0.73
171
0.015
0.021
0.027
33
- 0.83
0.017
0.022
0.027
31
- 0.8
V
A
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
=
−
2.5V, I
D
=
− 9.8
A
V
GS
=
−
1.8V, I
D
=
− 2A
Ω
Forward Transconductance
Diode Forward Voltage
a
a
g
fs
V
SD
V
DS
=
−
15V, I
D
=
−
11A
I
S
=
−
3.2A, V
GS
= 0V
S
V
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
=
−
3.2A, di/dt = 100 A/µs
V
DD
=
−
10V, R
L
= 10Ω
I
D
≅ −
1A, V
GEN
=
−
4.5V, R
G
= 6Ω
V
DS
=
−
10V, V
GS
=
−
4.5V, I
D
=
−
11A
33
5.9
5.2
34
42
52
78
30
29
5.9
5.2
23
45
130
95
30
ns
nC
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 71638
31-May-01
SPICE Device Model Si7401DN
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 71638
31-May-01
www.vishay.com
3
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