SPICE Device Model Si7392ADP
Vishay Siliconix
N-Channel Reduced Q
g
, Fast Switching WFET
CHARACTERISTICS
•
N-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 73517
S-61151Rev. B, 26-Jun-06
www.vishay.com
1
SPICE Device Model Si7392ADP
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
V
GS(th)
I
D(on)
r
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= 250
µA
V
DS
≥
5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 12.5A
V
GS
= 4.5 V, I
D
= 10A
V
DS
= 15 V, I
D
= 12.5A
I
S
= 2.7A
1.9
686
0.006
0.009
45
0.73
0.006
0.009
46
0.73
V
A
Ω
S
V
Symbol
Test Condition
Simulated
Data
Measured
Data
Unit
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
V
DS
= 15 V, V
GS
= 10 V, I
D
= 12.5A
V
DS
= 15 V, V
GS
= 0 V, f = 1 MHz
1626
360
136
22
11
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 12.5A
3.7
3.1
1465
360
150
25
12
3.7
3.1
nC
pF
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 73517
S-61151Rev. B, 26-Jun-06
SPICE Device Model Si7392ADP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 73517
S-61151Rev. B, 26-Jun-06
www.vishay.com
3
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