SPICE Device Model Si6966EDQ
Vishay Siliconix
N-Channel 2.5-V (G-S) MOSFET, ESD Protected
CHARACTERISTICS
•
N-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0 to 5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 70074
22-Oct-04
www.vishay.com
1
SPICE Device Model Si6966EDQ
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
Symbol
V
GS(th)
I
D(on)
r
DS(on)
g
fs
V
SD
Test Conditions
V
DS
= V
GS
, I
D
= 250
µA
V
DS
≥
5 V, V
GS
= 4.5 V
V
GS
= 4.5 V, I
D
= 5.2 A
V
GS
= 2.5 V, I
D
= 4.5 A
V
DS
= 10 V, I
D
= 5.2 A
I
S
= 1.25 A, V
GS
= 0 V
I
S
= 1.25 A, V
GS
= 0 V, T
j
= 125°C
Typical
0.923
120
0.02
0.027
19.5
0.65
0.57
Unit
V
A
Ω
S
V
Drain-Source On-State Resistance
a
Forward Transconductance
a
Schottky Diode Forward Voltage
a
Dynamic
b
Total Gate Charge
b
Gate-Source Charge
b
Gate-Drain Charge
b
Q
g
Q
gs
Q
gd
t
d(on)
t
r
b
13.4
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 5.2 A
2.1
5.7
0.35
V
DD
= 10 V, R
L
= 10
Ω
I
D
≅
1 A, V
GEN
= 4.5 V, R
G
= 6
Ω
76
131
290
I
F
= 1.25 A, di/dt = 100 A/µs
210
ns
nC
Turn-On Delay Time
b
Rise Time
b
Turn-Off Delay Time
Fall Time
b
t
d(off)
t
f
t
rr
Source-Drain Reverse Recovery Time
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 70074
22-Oct-04
SPICE Device Model Si6966EDQ
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 70074
22-Oct-04
www.vishay.com
3
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