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SPICE Device Model Si6801DQ
Vishay Siliconix
N- and P-Channel Dual Enhancement-Mode MOSFET
CHARACTERISTICS
•
N- and P-Channel Vertical DMOS
•
Macro Model (Subcircuit Model)
•
Level 3 MOS
•
Apply for both Linear and Switching Application
•
Accurate over the
−55
to 125°C Temperature Range
•
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n- and p-channel vertical DMOS. The model
subcircuit
is
extracted
and
optimized
over
the
−55
to 125°C temperature ranges under the pulsed 0 to 5V gate
drive. The saturated output impedance is best fit at the gate bias
near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
a
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71023
22-May-04
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Vishay Siliconix
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Parameter
Static
Gate Threshold Voltage
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SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Symbol
Test Conditions
V
DS
= V, V
GS
, I
D
= 250
µA
V
DS
= V, V
GS
, I
D
=
−250 µA
V
DS
5 V, V
GS
= 4.5 V
V
DS
=
−5
V, V
GS
=
−4.5
V
V
GS
= 4.5 V, I
D
= 1.9 A
Drain-Source On-State Resistance
a
Typical
Unit
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
1.02
V
1.15
23
A
18
0.112
0.154
0.149
0.217
5
S
4.1
0.77
−0.77
V
Ω
V
GS(th)
On-State Drain Current
a
I
D(on)
r
DS(on)
V
GS
=
−4.5
V, I
D
=
−1.7
A
V
GS
= 3 V, I
D
= 1.5 A
V
GS
=
−3
V, I
D
=
−1.3
A
Forward Transconductance
a
g
fs
V
DS
= 15 V, I
D
= 1.9 A
V
DS
=
−15
V, I
D
=
−1.7
A
I
S
= 1 A, V
GS
= 0 V
I
S
=
−1
V, V
GS
= 0 V
Diode Forward Voltage
a
V
SD
Dynamic
b
Total Gate Charge
Q
g
N-Channel
V
DS
= 3.5 V, V
GS
= 4.5 V, I
D
= 0.3 A
P-Channel
V
DS
=
−3.5
V, V
GS
=
−4.5
V, I
D
=
−0.3
A
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
Turn-On Delay Time
t
d(on)
N-Channel
V
DD
= 3.5 V, R
L
= 11.5
Ω
I
D
≅
0.3 A, V
GEN
= 4.5 V, R
G
= 6
Ω
P-Channel
V
DD
=
−3.5
V, R
L
= 11.5
Ω
I
D
≅ −0.3
A, V
GEN
=
−4.5
V, R
G
= 6
Ω
N-Ch
P-Ch
Rise Time
t
r
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
Source-Drain Reverse Recovery Time
t
rr
I
F
= 1 A, di/dt = 100 A/µs
I
F
=
−1
A, di/dt = 100 A/µs
N-Ch
P-Ch
1.6
3
0.41
0.76
0.26
0.70
5.2
6
6.2
10
9
ns
11
15
22
31
30
nC
Gate-Source Charge
Q
gs
Gate-Drain Charge
Q
gd
Turn-Off Delay Time
t
d(off)
Fall Time
t
f
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
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Document Number: 71023
22-May-04
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SPICE Device Model Si6801DQ
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
N-CHANNEL MOSFET
Document Number: 71023
22-May-04
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