b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation
process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder intercon-
nection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71053
S-21251—Rev. A, 05-Aug-02
www.vishay.com
2-7
Si5902DC
Vishay Siliconix
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
V
GS(th)
I
GSS
I
DSS
I
D(on)
r
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= 250
mA
V
DS
= 0 V, V
GS
=
20
V
V
DS
= 24 V, V
GS
= 0 V
V
DS
= 24 V, V
GS
= 0 V, T
J
= 85_C
V
DS
≥
5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 2.9 A
V
GS
= 4.5 V, I
D
= 2.2 A
V
DS
= 15 V, I
D
= 2.9 A
I
S
= 0.9 A, V
GS
= 0 V
10
0.072
0.120
20
0.8
1.2
0.085
0.143
1.0
100
1
5
V
nA
mA
A
Ω
S
V
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= 0.9 A, di/dt = 100 A/ms
V
DD
= 15 V, R
L
= 15
Ω
I
D
≅
1 A, V
GEN
= 10 V, R
G
= 6
Ω
V
DS
= 15 V, V
GS
= 10 V, I
D
= 2.9 A
5
0.8
1.0
7
12
12
7
40
11
18
18
11
80
ns
7.5
nC
Notes
a. Pulse test; pulse width
≤
300
ms,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
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