The PowerPAK ChipFET is a leadless package. The end of the lead terminal is
exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be
guaranteed and is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 105 °C/W for both channels.
Document Number: 73529
S-81449-Rev. B, 23-Jun-08
www.vishay.com
1
t
≤
5s
Steady State
Symbol
R
thJA
R
thJC
N-Channel
Typ.
Max.
45
55
12
15
P-Channel
Typ.
Max.
45
55
12
15
Unit
Si5517DU
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate Threshold Voltage
Gate-Body Leakage
V
DS
ΔV
DS
/T
J
ΔV
GS(th)
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, I
D
= - 1 mA
I
D
= 250 µA
I
D
= - 250 µA
I
D
= 250 µA
I
D
= - 250 µA
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= 0 V, V
GS
= ± 8 V
V
DS
= 20 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= - 20 V, V
GS
= 0 V
V
DS
= 20 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
= - 20 V, V
GS
= 0 V, T
J
= 55 °C
On-State Drain Current
b
I
D(on)
V
DS
≤
5 V, V
GS
= 4.5 V
V
DS
≤
- 5 V, V
GS
= - 4.5 V
V
GS
= 4.5 V, I
D
= 4.4 A
V
GS
= - 4.5 V, I
D
= - 3.3 A
Drain-Source On-State Resistance
b
R
DS(on)
V
GS
= 2.5 V, I
D
= 4.1 A
V
GS
= - 2.5 V, I
D
= - 2.8 A
V
GS
= 1.8 V, I
D
= 1.8 A
V
GS
= - 1.8 V, I
D
= - 0.76 A
Forward Transconductance
b
Dynamic
a
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
iss
C
oss
C
rss
P-Channel
V
DS
= - 10 V, V
GS
= 0 V, f = 1 MHz
V
DS
= 10 V, V
GS
= 8 V, I
D
= 4.4 A
Total Gate Charge
Q
g
V
DS
= - 10 V, V
GS
= - 8 V, I
D
= - 4.6 A
N-Channel
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.4 A
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Q
gs
Q
gd
R
g
N-Ch
N-Channel
V
DS
= 10 V, V
GS
= 0 V, f = 1 MHz
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
520
455
100
105
60
65
10.5
9.1
6
5.5
0.91
0.75
0.7
1.5
1.9
8
Ω
16
14
9
8.5
nC
pF
g
fs
V
DS
= 10 V, I
D
= 4.4 A
V
DS
= - 10 V, I
D
= - 3.3 A
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
20
- 15
0.032
0.060
0.037
0.083
0.0455
0.108
22
9
0.039
0.072
0.045
0.100
0.055
0.131
S
Ω
0.4
- 0.4
20
- 20
17
- 20
- 2.6
2.4
1
-1
100
- 100
1
-1
10
- 10
A
µA
V
nA
mV/°C
V
Symbol
Test Conditions
Min.
Typ.
a
Max.
Unit
P-Ch
P-Channel
V
DS
= - 10 V, V
GS
= - 4.5 V, I
D
= - 1.8 A N-Ch
P-Ch
f = 1 MHz
N-Ch
P-Ch
www.vishay.com
2
Document Number: 73529
S-81449-Rev. B, 23-Jun-08
Si5517DU
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Dynamic
a
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode
Current
Pulse Diode Forward Current
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
a
Symbol
Test Conditions
N-Ch
N-Channel
V
DD
= 10 V, R
L
= 2.8
Ω
I
D
≅
3.6 A, V
GEN
= 4.5 V, R
g
= 1
Ω
P-Ch
N-Ch
P-Ch
Min.
Typ.
a
20
8
65
35
40
40
10
55
5
5
12
15
26
30
8
45
Max.
30
15
100
55
60
60
15
85
10
10
20
25
40
45
15
70
6.9
- 6.9
20
- 15
Unit
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
N-Ch
P-Channel
P-Ch
V
DD
= - 10 V, R
L
= 2.7
Ω
I
D
≅
- 3.7 A, V
GEN
= - 4.5 V, R
g
= 1
Ω
N-Ch
P-Ch
N-Ch
N-Channel
V
DD
= 10 V, R
L
= 2.8
Ω
I
D
≅
3.6 A, V
GEN
= 8 V, R
g
= 1
Ω
P-Channel
V
DD
= - 10 V, R
L
= 2.7
Ω
I
D
≅
- 3.7 A, V
GEN
= - 8 V, R
g
= 1
Ω
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
I
S
= 1.2 A, V
GS
= 0 V
I
S
= - 1.0 A, V
GS
= 0 V
N-Ch
P-Ch
N-Ch
P-Ch
N-Channel
N-Ch
I
F
= 1.2 A, dI/dt = 100 A/µs, T
J
= 25 °C
P-Ch
P-Channel
I
F
= - 1 A, dI/dt = 100 A/µs, T
J
= 25 °C
N-Ch
P-Ch
N-Ch
P-Ch
ns
I
S
I
SM
V
SD
t
rr
Q
rr
t
a
t
b
T
C
= 25 °C
A
0.8
- 0.8
45
30
21
15
29
11
16
19
1.2
- 1.2
70
60
32
30
V
ns
nC
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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