d. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation
process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder
interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f.
Maximum under steady state conditions is 90
_C/W
for both channels.
Document Number: 73629
S–60417—Rev. A, 20-Mar-06
www.vishay.com
1
Si5509DC
New Product
SPECIFICATIONS (T
J
= 25
_C
UNLESS OTHERWISE NOTED)
Parameter
Static
V
GS
= 0 V, I
D
= 250
mA
Drain-Source
Drain Source Breakdown Voltage
V
DS
V
GS
= 0 V, I
D
= –250
mA
I
D
= 250
mA
I
D
= –250
mA
I
D
= 250
mA
I
D
= –250
mA
V
DS
= V
GS
, I
D
= 250
mA
V
DS
= V
GS
, I
D
= –250
mA
V
DS
= 0 V, V
GS
=
"12
V
V
V
DS
= 20 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= –20 V, V
GS
= 0 V
V
DS
= 20 V, V
GS
= 0 V, T
J
= 55
_C
V
DS
= –20 V, V
GS
= 0 V, T
J
= 55
_C
On-State
On State Drain Current
b
V
DS
v
5 V, V
GS
= 4.5 V
I
D( )
D(on)
V
DS
v
–5 V, V
GS
= –4.5 V
V
GS
= 4.5 V, I
D
= 5.0 A
Drain-Source On-State
Drain Source On State Resistance
b
r
DS( )
DS(on)
V
GS
= –4.5 V, I
D
= –3.9 A
V
GS
= 2.5 V, I
D
= 3.9 A
V
GS
= –2.5 V, I
D
= –2.9 A
Forward Transconductance
b
g
f
fs
V
DS
= 10 V, I
D
= 5.0 A
V
DS
= –10 V, I
D
= –3.9 A
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
10
–15
0.043
0.074
0.068
0.128
10.4
8.2
S
0.052
0.090
0.084
0.160
W
A
0.7
–0.7
20
–20
18.4
–15.1
–3.4
2.2
2
–2
100
–100
1
–1
10
–10
mA
nA
V
mV/_C
Vishay Siliconix
Symbol
Test Condition
Min
Typ
a
Max
Unit
V
DS
Temperature Coefficient
DV
DS
/T
J
V
GS( h)
Temperature Coefficient
GS(th)
DV
GS( h)
/T
J
GS(th)
Gate Threshold Voltage
V
GS( h)
GS(th)
I
GSS
Gate-Body
Gate Body Leakage
Dynamic
a
N-Ch
Input Capacitance
C
iiss
C
oss
C
rss
V
DS
= 10 V, V
GS
= 5 V, I
D
= 4.0 A
Total Gate Charge
Q
g
V
DS
= –10 V, V
GS
= –5 V, I
D
= –3.9 A
N-Channel
V
DS
= 10 V, V
GS
= 0 V, f = 1 MHz
P Channel
P-Channel
V
DS
= –10 V, V
GS
= 0 V, f = 1 MHz
Reverse Transfer Capacitance
P-CH
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N-Ch
P-Ch
N Ch
N-Ch
N-Channel
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.0 A
Gate-Source
Gate Source Charge
Q
gs
P Channel
P-Channel
V
DS
= –10 V, V
GS
= –4.5 V, I
D
= –3.9 A
Gate-Drain
Gate Drain Charge
Q
gd
d
R
g
f = 1 MHz
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
455
300
85
95
50
65
4.4
4.1
3.8
3.9
0.9
0.7
0.95
1.25
1.9
8
W
6.6
6.2
5.7
5.9
nC
pF
Output Capacitance
Gate Resistance
www.vishay.com
2
Document Number: 73629
S–60417—Rev. A, 20-Mar-06
Si5509DC
New Product
SPECIFICATIONS (T
J
= 25
_C
UNLESS OTHERWISE NOTED)
Parameter
Dynamic
a
Turn-On
Turn On Delay Time
t
d( )
d(on)
t
r
t
d( ff)
d(off)
t
f
N-Channel
N Channel
V
DD
= 10 V, R
L
=2.5
W
I
D
^
4.0 A, V
GEN
= 4.5 V, R
g
= 1
W
P Channel
P-Channel
V
DD
= –10 V, R
L
= 3.2
W
I
D
^
–3 14 A, V
GEN
= –4.5 V, R
g
= 1
W
–3.14 A
–4 5 V
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
N Ch
N-Ch
P-Ch
6
8
95
75
12
25
6
60
9
12
143
113
18
38
9
90
ns
Vishay Siliconix
Symbol
Test Condition
Min
Typ
a
Max
Unit
Rise Time
Turn-Off
Turn Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source Drain Diode Current
Source-Drain
Pulse Diode Forward Current
a
I
S
I
SM
I
S
= 2.4 A, V
GS
= 0 V
Body Diode Voltage
V
SD
t
rr
Q
rr
t
a
t
b
N-Channel
I
F
= 2.4 A, di/dt = 100 A/ms, T
J
= 25
_C
P Channel
P-Channel
I
F
= –1.5 A, di/dt = –100 A/ms, T
J
= 25
_C
I
S
= –1.5 A, V
GS
= 0 V
T
C
= 25
_C
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
Body Diode Reverse Recovery Time
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
Reverse Recovery Rise Time
P-Ch
0.8
–0.8
12
18
5
8
7.5
14
4.5
4
ns
3.75
–3.75
10
–15
1.2
–1.2
18
27
8
12
nC
ns
V
A
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width
v
300
ms,
duty cycle
v
2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
