b. See Reliability Manual for profile. The ChipFET/PowerPAK is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the
singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder
interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71056
S-21251—Rev. B, 05-Aug-02
www.vishay.com
2-1
Si5504DC
Vishay Siliconix
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
mA
V
DS
= V
GS
, I
D
= -250
mA
V
DS
= 0 V, V
GS
=
"20
V
"
V
DS
= 24 V, V
GS
= 0 V
V
DS
= -24 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 24 V, V
GS
= 0 V, T
J
= 85_C
V
DS
= -24 V, V
GS
= 0 V, T
J
= 85_C
On-State Drain Current
a
V
DS
w
5 V, V
GS
= 10 V
I
D(on)
V
DS
p
-5 V, V
GS
= -10 V
V
GS
= 10 V, I
D
= 2.9 A
Drain-Source On-State Resistance
a
V
GS
= -10 V, I
D
= -2.1 A
r
DS(on)
V
GS
= 4.5 V, I
D
= 2.2 A
V
GS
= -4.5 V, I
D
= -1.6 A
Forward Transconductance
a
V
DS
= 15 V, I
D
= 2.9 A
g
fs
V
DS
= -15 V, I
D
= -2.1 A
I
S
= 0.9 A, V
GS
= 0 V
V
SD
I
S
= -0.9 A, V
GS
= 0 V
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
10
-10
0.072
0.137
0.120
0.240
6
3
0.8
-0.8
1.2
-1.2
V
S
0.085
0.165
0.143
0.290
W
A
1.0
V
-1.0
"100
"100
1
-1
5
-5
mA
m
nA
Symbol
Test Condition
Min
Typ
Max
Unit
Gate-Body Leakage
I
GSS
Diode Forward Voltage
a
Dynamic
b
N-Ch
Total Gate Charge
Q
g
N-Channel
V
DS
= 15 V, V
GS
= 10 V, I
D
= 2.9 A
Gate-Source Charge
Q
gs
P-Channel
V
DS
= -15 V, V
GS
= -10 V, I
D
= -2.1 A
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
Turn-On Delay Time
t
d(on)
N-Channel
V
DD
= 15 V, R
L
= 15
W
I
D
^
1 A, V
GEN
= 10 V, R
G
= 6
W
P-Channel
V
DD
= -15 V, R
L
= 15
W
I
D
^
-1 A, V
GEN
= -10 V, R
G
= 6
W
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
Fall Time
Source-Drain
Reverse Recovery Time
t
f
I
F
= 0.9 A, di/dt = 100 A/ms
t
rr
I
F
= -0.9 A, di/dt = 100 A/ms
P-Ch
N-Ch
P-Ch
5
5.5
0.8
nC
1.2
1.0
0.9
7
8
12
11
12
14
7
8
40
40
11
12
18
18
18
21
11
12
80
80
ns
7.5
6.6
Gate-Drain Charge
Q
gd
Rise Time
t
r
Turn-Off Delay Time
t
d(off)
Notes
a. Pulse test; pulse width
v
300
ms,
duty cycle
v
2%,
b. Guaranteed by design, not subject to production testing.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
