b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singula-
tion process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder inter-
connection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 72261
S-31265—Rev. A, 16-Jun-03
www.vishay.com
1
Si5473DC
Vishay Siliconix
New Product
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
V
GS(th)
I
GSS
I
DSS
I
D(on)
V
DS
= V
GS
, I
D
= - 250
mA
V
DS
= 0 V, V
GS
=
"8
V
V
DS
= - 9.6 V, V
GS
= 0 V
V
DS
= - 9.6 V, V
GS
= 0 V, T
J
= 85_C
V
DS
p
- 5 V, V
GS
= - 4.5 V
V
GS
= - 4.5 V, I
D
= - 5.9 A
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= - 2.5 V, I
D
= - 5.3 A
V
GS
= - 1.8 V, I
D
= - 2.2 A
Forward Transconductance
a
Diode Forward Voltage
a
g
fs
V
SD
V
DS
= - 5 V, I
D
= - 5.9 A
I
S
= - 1.1 A, V
GS
= 0 V
- 20
0.022
0.028
0.036
20
- 0.8
- 1.2
0.027
0.0335
0.045
S
V
W
- 0.40
- 1.0
"100
-1
-5
V
nA
mA
A
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= - 1.1 A, di/dt = 100 A/ms
V
DD
= - 6 V, R
L
= 6
W
I
D
^
- 1 A, V
GEN
= - 4.5 V, R
G
= 6
W
V
DS
= - 6 V, V
GS
= - 4.5 V, I
D
= - 5.9 A
21
3.1
6.0
25
50
145
90
70
40
75
220
135
105
ns
32
nC
Notes
a. Pulse test; pulse width
v
300
ms,
duty cycle
v
2%.
b. Guaranteed by design, not subject to production testing.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
