c. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singula-
tion process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder inter-
connection.
d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71364
S-21251—Rev. C, 05-Aug-02
www.vishay.com
2-1
Si5463EDC
Vishay Siliconix
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
V
GS(th)
I
GSS
I
DSS
I
D(on)
V
DS
= V
GS
, I
D
= --250
mA
V
DS
= 0 V, V
GS
=
4.5
V
V
DS
= --16 V, V
GS
= 0 V
V
DS
= --16 V, V
GS
= 0 V, T
J
= 85_C
V
DS
--5
V, V
GS
= --4.5 V
V
GS
= --4.5 V, I
D
= --4.0 A
Drain-Source On-State
Drain Source On State Resistance
a
r
DS( )
DS(on)
V
GS
= --3.6 V, I
D
= --3.5 A
V
GS
= --2.5 V, I
D
= --3.0 A
V
GS
= --1.8 V, I
D
= --1.5 A
Forward Transconductance
a
Diode Forward Voltage
a
g
fs
V
SD
V
DS
= --5 V, I
D
= --4.0 A
I
S
= --1.0 A, V
GS
= 0 V
--15
0.051
0.056
0.070
0.100
10
--0.75
--1.2
0.062
0.068
0.085
0.120
S
V
Ω
--0.45
1.5
--1
--5
A
mA
V
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
DD
= --10 V, R
L
= 10
Ω
I
D
≅
--1 A, V
GEN
= --4.5 V, R
G
= 6
Ω
V
DS
= --10 V, V
GS
= --4.5 V, I
D
= --4.0 A
9.7
2.7
1.4
1.85
3.2
1.9
3.2
2.5
4.5
2.5
4.5
ms
15
nC
Notes
a. Pulse test; pulse width
≤
300
ms,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
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