Si5022/Si5023
P
RELIMINARY
D
ATA
S
HEET
M
ULTI
-R
ATE
SONET/SDH CDR IC
Features
WITH
L
IMITING
A
MP
H
igh Speed Clock and Data Recovery device with Integrated Limiting Amp:
!
!
!
!
!
Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
DSPLL™ Technology
Low Power—370 mW (TYP)
Small Footprint: 5 mm x 5 mm
Bit-Error-Rate Alarm
!
!
!
!
!
!
External Reference Not Required
Jitter Generation 3.0 mUI
RMS
(TYP)
Loss-of-signal Level Alarm
Data Slicing Level Control
10 mV
PP
Differential Sensitivity
2.5 V (Si5022) or 3.3 V (Si5023) Supply
Ordering Information:
See page 14.
Applications
!
SONET/SDH/ATM Routers
!
Add/Drop Multiplexers
!
Digital Cross Connects
!
Gigabit Ethernet Interfaces
!
SONET/SDH Test Equipment
!
Optical Transceiver Modules
!
SONET/SDH Regenerators
!
Board Level Serial Links
Pin Assignments
Si5022/23
BER_ALM
CLKOUT+
23
The Si5022/23 is a fully integrated, high performance limiting amp and clock and
data recovery (CDR) IC for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided
for OC-48/STM-16 applications that employ forward error correction (FEC). An
external reference clock is not required; applications with or without an external
reference clock are supported. Silicon Laboratories’ DSPLL
™
technology
eliminates sensitive noise entry points thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5022/23 represents a new standard in low jitter, low power, small size, and
integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or
2.5 V (Si5022) supply over the industrial temperature range (–40°C to 85°C).
28
27
26
VDD
Description
NC
RATESEL0
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
1
2
3
4
5
6
7
8
25
24
CLKOUT–
22
21
20
19
CLKDSBL
BER_LVL
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
TDI
GND
Pad
18
17
16
15
9
10
11
12
13
14
LOS
DSQLCH
DIN+
LTR
VDD
Top View
Functional Block Diagram
DSQLCH
Squelch
C ontrol
R etim er
2
BU F
D O U T+
D O U T–
CLKDSBL
D IN +
D IN –
2
Lim iting
AM P
D S P LL
TM
Phase-Locked
Loop
2
BU F
C L K O U T+
C L K O U T–
LO L
C ontrol
L O S _L V L
2
R E S E T /C AL
Bias G en
S L IC E _L V L
LO S
BER_LVL
LTR
R ATS E L [1:0]
REXT
REFCLK+
REFCLK–
B E R _ AL M
(Optional)
Preliminary Rev. 0.46 5/01
Copyright © 2001 by Silicon Laboratories
Si5022/23-DS046
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
DIN–
VDD
S i5 02 2/ S i5 023
2
Preliminary Rev. 0.46
Si5022/Si5023
T
A B L E
Section
OF
C
ONTENTS
Page
4
5
11
11
11
11
11
12
12
12
12
13
13
13
14
14
14
14
14
14
14
16
17
20
21
22
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss-of-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions: Si5022/23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.46
3
S i5 02 2/ S i5 023
Detailed Block Diagram
LOS
B ER _LV L
B E R _A L M
LTR
R AT E S E L [0:1 ]
D SQ LC H
L O S _L V L
S ig n a l
D e tec t
BER
M o n ito r
R e tim e
D O U T+
D O U T–
D IN +
L im itin g
Am p
D IN +
n
P h as e
D e te cto r
A/D
DSP
VCO
CLK
D ivid ers
C LK O U T+
C LK O U T–
CLK_DSBL
S L IC E _L V L
S lic in g
C o n tro l
R E FC LK ±
(o p tio n al)
Lock
D e te c tio n
LOL
REXT
B ia s
G en era tio n
C a lib ra tio n
R E S E T /C AL
Figure 1. Detailed Block Diagram
4
Preliminary Rev. 0.46
Si5022/Si5023
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5022 Supply Voltage
2
Si5023 Supply
Voltage
2
Symbol
T
A
V
DD
V
DD
Test Condition
Min
1
–40
2.375
3.135
Typ
25
2.5
3.3
Max
1
85
2.625
3.465
Unit
°C
V
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless
otherwise stated.
2.
The Si5022/23 specifications are guaranteed when using the recommended application circuit (including
component tolerance) of Figure 5 on page 10.
V
SIGNAL+
SIGNAL–
V
IS
t
A. Operation with Single-Ended Inputs
V
SIGNAL+
SIGNAL–
0.5 V
ID
(SIGNAL+) – (SIGNAL–)
V
ID
t
B. Operation with Differential Inputs and Outputs
Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
Preliminary Rev. 0.46
5
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