controls the synchronous function for light load conditions.
The Si4724CY is packaged in Vishay Siliconix’s high
performance LITTLE FOOTR SO-16 package.
FUNCTIONAL BLOCK DIAGRAM
V
DD
BOOT
D
1
Level Shift
Undervoltage
Lockout
V
DD
IN
SYNC EN
Q
1
S
1
D
2
Q
2
+
-
GND
S
2
V
REF
Document Number: 71863
S-03922—Rev. D, 19-May-03
www.vishay.com
1
Si4724CY
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Logic Supply
Logic Inputs
Drain Voltage
Bootstrap Voltage
Synchronous Pin Voltage
T
A
= 25_C
Continuous Drain Current
T
A
=70_C
T
A
= 25_C
T
A
=70_C
Maximum Power Dissipation
a
Driver
Operating Junction and Storage Temperature Range
MOSFETs
T
j
, T
stg
Symbol
V
DD
V
IN
V
D1
V
BOOT
V
SYNC
I
D1
I
D2
P
D
Steady State
7
- 0.7 to V
DD
+ 0.3
30
V
S1
+ 7
- 0.7 to V
DD
+0.3
5.1
4.09
6.5
5.2
1.2
- 65 to 125
- 65 to 150
Unit
V
A
W
_C
Notes
a. Surface mounted on 1” x1” FR4 board, full copper two sides.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Drain Voltage
Logic Supply
Input Logic High Voltage
Input Logic Low Voltage
Bootstrap Capacitor
Ambient Temperature
Symbol
V
D1
V
DD
V
IH
V
IL
C
BOOT
T
A
Steady State
0 to 30
4.5 to 5.5
0.7
V
DD
to V
DD
V
DD
Unit
V
- 0.3 to 0.3
100 n to 1
m
- 40 to 85
F
_C
THERMAL RESISTANCE RATINGS
Parameter
Highside Junction-to-Ambient
a
Lowside Junction-to-Ambient
a
Highside Junction-to-Foot (Drain)
b
Lowside Junction-to-Foot (Drain)
b
Steady State
Symbol
R
thJA1
R
thJA2
R
thJF1
R
thJF2
Typical
85
68
28
19
Maximum
105
85
35
24
Unit
_C/W
Notes
a. Surface Mounted on 1” x 1” FR4 Board.
b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with
the thermal impedance of the PC board pads to ambient (R
thJA
= R
thJF
+ R
thPCB-A
). It can also be used to estimate chip temperature if power dissipation and
the lead temperature of a heat carrying (drain) lead is known.
www.vishay.com
2
Document Number: 71863
S-03922—Rev. D, 19-May-03
Si4724CY
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
p
Parameter
Power Supplies
Logic Voltage
Logic Current
V
DD
I
DD(EN)
I
DD(DIS)
V
DD
= 4.5 V, V
IN
= 4.5 V
V
DD
= 4.5 V, V
IN
= 0 V
4.5
280
220
5.5
500
500
V
mA
Limits
Min
Typ
Max
Unit
Symbol
T
A
= 25_C
4.5 V < V
DD
< 5.5 V, 4.5 V < V
D1
< 30 V
Logic Input
High
Logic Input Voltage (V
IN
)
Low
V
IH
V
IL
V
DD
= 4.5 V
- 40_C
¬T
A
¬85_C
3.15
- 0.3
2.3
2.25
0.8
V
Protection
Break-Before-Make Reference
Undervoltage Lockout
Undervoltage Lockout Hysteresis
V
BBM
V
UVLO
V
H
V
DD
= 5.5 V
SYNC = 4.5 V
3.75
2.4
4
0.4
4.25
V
MOSFET Drivers
Driver Impedance
R
DR1
R
DR2
Driver 1
V
DD
= 4 5 V
4.5
Driver 2
3
2
W
MOSFETs
Drain-Source Voltage
Drain-Source On-State
Drain Source On State Resistance
a
Diode Forward Voltage
a
V
DS
r
DS(on)1
r
DS(on)2
V
SD1
V
SD2
I
D
= 250
mA
V
DD
= 4.5 V, I
D
= 5 A
T
A
= 25_C
I
S
= 2 A V
GS
= 0 V
A,
Q1
Q2
Q1
Q2
30
30
24
0.7
0.7
37.5
29
1.1
1.1
V
mW
V
Dynamic
b
(Unless Specified—F
s
= 250 kHz, V
IN
= 12 V. V
DD
= 5 V, I = 5 A, Refer to Switching Test Setup)
Turn-Off
Turn Off Delay
Dt
Source-Drain Reverse Recovery
Time—Q
2
t
d(off)1
t
d(off)2
Dt
1-2
Dt
2-1
t
frr
See Timing Diagram
V
IN
to G
1
V
IN
to G
2
G
1
to G
2
G
2
to G
1
I
F
2.7 A, di/dt = 100 A/ms
28
17
16
38
50
56
40
32
80
80
ns
Notes
a. Pulse test: pulse width
v300
ms;
duty cycle
v
2%.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SCHOTTKY SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Forward Voltage Drop
Symbol
V
F
Test Condition
I
F
= 1.0 A
I
F
= 1.0 A, T
J
= 125_C
V
r
= 30 V
V
r
= 30 V, T
J
= 100_C
V
r
= - 30 V, T
J
= 125_C
V
r
= 10 V
Min
Typ
0.47
0.36
0.004
0.7
3.0
50
Max
0.50
0.42
0.100
10
20
Unit
V
Maximum Reverse Leakage Current
g
I
rm
mA
Junction Capacitance
C
T
pF
Document Number: 71863
S-03922—Rev. D, 19-May-03
www.vishay.com
3
Si4724CY
Vishay Siliconix
APPLICATION CIRCUIT
0 V to 30 V
5V
V
DD
Si4724
C
BOOT
D
1
Q
1
MOSFET
Drive Circuitry
with
Break-Before-
Make
S
1
D
2
C
BOOT
V
OUT
+
SYNC EN
DC-DC
Controller
IN
GND
Q
2
S
2
GND
GND
Power Up Sequence:
Ensure V
DD
is within spec before allowing IN or SYNC EN to be set high.
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