Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
−55
to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72172
S-51095Rev. B, 13-Jun-05
www.vishay.com
1
SPICE Device Model Si4464DY
Vishay Siliconix
SPECIFICATIONS (T
J
= 25°C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
b
Symbol
Test Condition
Simulated
Data
2.9
26
0.192
0.199
6.1
0.74
Measured
Data
Unit
V
GS(th)
I
D(on)
r
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= 250
µA
V
DS
≥
5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 2.2 A
V
GS
= 6 V, I
D
= 2.1 A
V
DS
= 15 V, I
D
= 2.2 A
I
S
= 2.1 A, V
GS
= 0 V
V
A
0.195
0.210
8
0.8
Ω
S
V
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= 2.1 A, di/dt = 100 A/µs
V
DD
= 100 V, R
L
= 100
Ω
I
D
≅
1 A, V
GEN
= 10 V, R
G
= 6
Ω
V
DS
= 100 V, V
GS
= 10 V, I
D
= 2.2 A
13
2.5
3.8
14
12
8
10
53
12
2.5
3.8
10
12
15
15
60
ns
nC
Notes
a. Pulse test; pulse width
≤
300
µs,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 72172
S-51095Rev. B, 13-Jun-05
SPICE Device Model Si4464DY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25°C UNLESS OTHERWISE NOTED)
Document Number: 72172
S-51095Rev. B, 13-Jun-05
www.vishay.com
3
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
SMT贴片机是表面贴装技术（Surface Mount Technology）中的重要设备，它的性能状态对电子制造的质量和效率有着决定性的影响。因此，对SMT贴片机的主要指标性能进行定期检测非常重要。以下是一些主要的检测项目： 定位精度：定位精度是SMT贴片机的核心性能指标，它直接影响到贴片的准确性。通常，我们通过重复测量贴片机在X、Y轴上的移动误差来检测其定位精度。 贴片速度：贴片速度...[详细]
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
