SED1600
CMOS 80-SEGMENT LCD DRIVER
s
DESCRIPTION
High Voltage Output
•
80-bit to 1/300 Display Duty
•
1/100
The SED1600 is a dot matrix LCD segment (column) driver for driving a high-capacity LCD panel at duty
cycles higher than 1/100 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1600, the LCD driving voltage, V0, is isolated from the V
DD
supply. This provides the
ability to adjust the offset bias independently of V
DD
. These unique features allow the SED1600 to interface
with a variety of LCD panels. The SED1600 does not require a controller to output an enable signal to
implement daisy chain technology. This provides for easy interfacing with the LCD controllers such as the
SED1330, SED1351, SED1335, or the SED1341.
The SED1600 is used in conjunction with the SED1610 (86-row driver), SED1630 (68-bit row driver),
SED1631 (100-row driver), SED1632 (86-bit row driver), SED1633 (100-bit row driver), and SED1634 (100-
bit driver) to drive a large-capacity dot matrix LCD panel.
s
FEATURES
•
Low-power CMOS technology
•
80-bit segment (column) driver
•
High-speed 4-bit data bus with enable chain tech-
nology
•
Duty cycle ............................... 1/100 to 1/300
•
Shift clock frequency .............. 6MHz max
•
Ability to adjust offset bias of the LCD source from
V
DD
•
Daisy chain enable support
•
Selectable output shift direction
•
No enable signal by controller is required
•
Wide range of LCD voltage .... –12 to –28V
•
Supply voltage ........................ 5.0V
±
10%
•
Package ..... QFP5-100 pin (F )
AA
DIE:
Al pad chip (D
AA
)
Au bump (D
AB
)
s
SYSTEM BLOCK DIAGRAM
D0 ~ D3
XSCL
LP, FR
YSCL
YD
LCD
CONTR
SED1600F
(1)
80
SED1600F
(n)
80
ROW
DRIVER
100~300
n*80 SEG
DUTY: 1/100 ~ 1/300
469
SED1600
s
BLOCK DIAGRAM
V
DD
V
SS
V0
V2
V3
V5
FR
Level Shifter
80 bit
Voltage
Control
LCD Driver
80 bit
LP
Register 2
80 bit
D0
D1
D2
D3
SHL
EIO1
EIO2
XSCL
Data
Control
4
Register 1
Enable
Control
ø1 ø2
Clock Generator
s
PINOUT
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
*
EIO2
D0
D1
D2
D3
NC
NC
NC
NC
V
DD
V
SS
V0
V2
V3
V5
SHL
XSCL
LP
FR
EIO1
80
75
70
65
60
55
SEG79
ø20
SEG0
SEG1
SEG2
50
85
45
90
Index
95
SED1600
40
35
100
1
5
10
15
20
25
30
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
* NC: No Connection
470
SED1600
s
PIN DESCRIPTION
Pin Name
SEG0 to SEG79
D0 TO D3
XSCL
LP
EI01, EI02
SHL
I/O
O
I
I
I
I/O
I
Function
LCD driving segment (column) outputs
Each output changes at the falling edge of LP.
Display data inputs.
Shift clock of display data (falling edge trigger).
Latch pulse of display data (falling edge trigger).
Enable I/O, which is controlled by SHL input . Output is reset by LP, and
automatically falls when 80 bits of data are taken in.
Shift direction selection and EIO pin I/O control.
When data (a, b, c, d) (e, f, g, h)······(w, x, y, z) are input to pins (D3, D2, D1,
D0) respectively, the following relation is established between the data and
segment outputs:
SHL
L
H
FR
V
DD
, V
SS
V0, V2, V3, V5
I
Power
Supplies
Power
Supplies
a
z
b
y
c
x
d
w
e
v
f
u
SEG
79 78 77 76 75 74 73 72 ...... 3
g
t
h ...... w
s ...... d
2
x
c
1
y
b
0
z
a
1
Output
Input
EIO
2
Input
Output
AC signal of LCD driving outputs.
Logic circuit power.
LCD driving power.
V
DD
: 0 V (GND)
V
SS
: –5.0 V
V
5
: –12 to –28 V
V
DD
≥
V0
≥
V2 > V3
≥
V5
s
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
•
(V
DD
= 0V)
Symbol
V
SS
V5
V0, V2, V3*
V
I
V
O
I
O
I
OSEG
P
D
T
opr
T
stg
T
sol
Ratings
–7.0 to +0.3
–30.0 to +0.3
V5 –0.3 to +0.3
V
SS
–0.3 to +0.3
V
SS
–0.3 to +0.3
20
20
300
–20 to +75
–65 to +150
260°C, 10 sec (at lead)
Unit
V
V
V
V
V
mA
mA
mW
°C
°C
—
Parameter
Supply voltage (1)
Supply voltage (2)
Supply voltage (2)
Input voltage (1)
Output voltage (1)
Output current (1)
Output current (2)
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperature, time
* V0, V2 and V3 must always satisfy the condition V
DD
≥
V0
≥
V2
≥
V3
≥
V5.
471
SED1600
•
DC Electrical Characteristics
Parameter
Symbol
V
SS
V5
—
V2
V3
V
IH
V
IL
V
OH
V
OL
I
LI
I
LI/O
I
OH
= –0.6 mA
I
OL
= 0.6 mA
V
SS
≤
V
I
≤
0 V
V
SS
≤
V
I
≤
0 V
V5 = –12.0 to –28.0 V
V
IH
= V
DD
, V
IL
= V
SS
–20.0V
Output resistance
R
SEG
Recommended value
Recommended value
Recommended value
Condition
(Unless otherwise specified, V
DD
= V0 = 0V,
V
SS
= –5.0 V
±
10%, T
a
= –20 to 85°C)
Pin
V
SS
V5
V0
V2
V3
EI01, EI02,
XSCL, LP,
D0 to D3,
FR, SHL
Min
–5.5
–28.0
–2.5
3/9·V5
V5
0.2V
SS
—
–0.4
—
—
—
—
—
—
—
—
Typ
–5.0
—
—
—
—
—
—
—
—
—
—
—
1.5
2.0
3.0
120
Max
–4.5
–12.0
–8.0
0
V0
6/9·V5
—
0.8V
SS
—
V
SS
+0.4
2.0
5.0
25
3.5
4.5
8.0
500
Unit
V
V
V
V
V
V
V
V
V
µA
µA
µA
Operating voltage
Recommended op. voltage
Minimum operating voltage
Operating voltage
Operating voltage
Operating voltage
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
Input leakage current
Stand–by current
EI01, EI02
D0 to D3, LP
XSCL, SHL, FR
EI01, EI02
I
DDS
V
DD
|
∆V
ON
|
= 0.5V
V5 –14.0V SEG0 to
SEG79
–8.0V
V
SS
= –5.0 V, V
IH
= V
DD
V
IL
= V
SS
,
f
XSCL
=1.92 MHz
f
LP
= 12 kHz, Frame period
= 60 Hz; Input data:
Inverted bit by bit, No-load
V
SS
= –5.0 V, V2 = –4.0 V
V3 = –16.0 V, V5 = –20.0 V
All other conditions are
same as I
SSO1
kΩ
Current dissipation (1)
I
SSO1
V
SS
µA
Current dissipation (2)
I
SSO2
V5
D0 to D3, LP
—
20
100
µA
pF
pF
Input capacitance
C
I
C
I/O
T
a
= 25°C
XSCL, SHL, FR
—
—
—
—
8.0
15.0
EI01, EI02
472
SED1600
•
AC Electrical Characteristics
Parameter
XSCL period
XSCL “H” pulse width
XSCL “L” pulse width
Data setup time
Data hold time
XSCL-rise to LP-rise time
XSCL-fall to LP-fall time
LP-rise to XSCL-rise time
LP-fall to XSCL-fall time
LP “H” pulse width
LP “L” pulse width
Allowable FR delay time
Enable “H” setup time
Enable “H” hold time
Enable “L” setup time
Enable “L” hold time
Input signal rise time
Input signal fall time
Symbol
Conditions
(V
SS
= –5.0 V
±10%,
T
a
= –20 to 85°C)
Min
166
70
70
60
40
0
70
70
70
70
230
–500
40
0
0
0
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
500
—
—
—
—
50*
50*
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CCL
t
WCLH
t
WCLL
t
DS
t
DH
t
LD
t
SL
t
LS
t
LH
t
WLPH
t
WLPL
t
DFR
t
suEIH
t
hEIH
t
suEIL
t
hEIL
t
r
t
f
t
r
,
t
f
≤
10 ns
* Note: The specifications for
t
r
and
t
f
are provided to prevent a malfunction which may occur when noise is mixed with a slow-
down signal. To assure high-speed XSCL, both
t
r
and
t
f
must satisfy the following relation:
t
CCL
– (
t
WCLH
+
t
WCLL
)
t
r
,
t
f
<
2
473
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