DATA SHEET
SBN1661G_M18,
SBN1661G_M02,
SBN0080G_S18,
SBN0080G_S02
Dot-matrix STN LCD Driver
with 32-row x 80-column
Display Data Memory
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v6.3)
2006 Aug 16
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
1
1.1
GENERAL
Description
The SBN1661G_X is a series of STN LCD SEGMENT/COMMON drivers. The series has four members:
•
the SBN1661G_M18,
•
the SBN1661G_M02,
•
the SBN0080G_S18, and
•
the SBN0080G_S02.
Both the SBN1661G_M18 and the SBN1661G_M02 can drive 16 COMMONs and 61 SEGMENTs and can be used as
master in a master-slave connection. They both have 32-row x 80-column Display Data Memory. Functionally, their only
difference is that the SBN1661G_M18 has an on-chip RC-type oscillator and can provide clock to slave, while the
SBN1661G_M02 does not have an on-chip oscillator and needs external clock source.
Both the SBN0080G_S18 and the SBN0080G_S02 are purely SEGMENT drivers. They do not have COMMON outputs
and are used for segment expansion in a master-slave connection. Both devices need either a master or an external
clock source to provide clock. The only difference between these two chips is their operating frequency. The
SBN0080G_S18’s operating frequency is 18 KHz, while the SBN0080G_S02’s operating frequency is 2KHz.
All four devices have on-chip Display Data Memory of 32-rows x 80-columns, for storing display data. Dot-matrix mapping
method is used to drive the LCD panel. Therefore, a bit of the Display Data Memory corresponds to a pixel on the LCD
panel. SEGMENT drivers provide display data to the LCD panel and COMMON drivers provide row-scanning signal.
All four devices have a set of internal registers. These internal registers must be properly programmed to ensure proper
operation of the devices.
Display on the LCD panel is controlled by a host microcontroller. All four devices communicate with the host
microcontroller via data bus and control bus. The data bus is 8-bit wide. The control bus are READ, WRITE, and
Chip Select. The host microcontroller can perform READ/WRITE operations to the internal registers and Display Data
RAM of all four devices. A wide variety of microcontrollers can easily interface with the devices, as the devices can accept
both 80-type interface timing and 68-type interface timing. The selection of interface timing is via the dual-function
RESET/IF pin.
2006 Aug 16
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data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
1.2
Features
•
Four members of the SBN1661G_X series:
– the SBN1661G_M18,
– the SBN1661G_M02,
– the SBN0080G_S18, and
– the SBN0080G_S02
•
16 COMMON, 61 SEGMENT STN LCD driver (the SBN1661G_M18 and the SBN1661G_M02).
•
80 SEGMENT STN LCD driver for expanding segment number (the SBN0080G_S18 and the SBN0080G_S02).
•
On-chip Display Data Memory: 32-row x 80-column (totally 2560 bits).
•
Dot Matrix Mapping between the Display Data Memory bit and LCD pixel.
•
A “0” stored in the Display Data Memory bit corresponds to an OFF-pixel on the LCD panel; a “1” stored in the Display
Data Memory bit corresponds to an ON-pixel on the LCD panel.
•
5-level external LCD bias.
•
Display duty cycle: 1/16, 1/32 for all four devices.
•
Two types of interface timing with a host microcontroller: the 80-type microcontroller and the 68-type microcontroller.
•
Dual function RESET/IF input for chip reset and selection of microcontroller interface timing.
•
8-bit parrallel data bus; READ, WRITE, CHIP SELECT control bus.
•
A set of internal registers: Display ON/OFF, Display Start Line, Static Drive ON/OFF, Memory Page Address, Memory
Column Address, Duty Selection, Memory Column/Segment mapping, and Status.
•
Display Data Read/Write commands and Software Reset command.
•
Read-Modify-Write command for block data transfer from the host microcontroller to the Display Data Memory.
•
Power-saving mode.
•
On-chip RC-type oscillator, requiring only an external resistor (the SBN1661G_M18).
•
Operating voltage range (V
DD
): 2.7 ~ 5.5 volts.
•
LCD bias voltage (V
LCD
=V5-V
DD
): -13 volts (max.).
•
Operating frequency range: 2 KHz, 18 KHz.
•
Operating temperature range: -20 to +75
°C.
•
Storage temperature range: -55 to +125
°C.
2006 Aug 16
3 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
1.3
Ordering information
Product types
Clock frequency
on-chip
SBN1661G_M18
SBN1661G_M02
SBN0080G_S18
SBN0080G_S02
18 KHz
External
18 KHz
2 KHz
18 KHz
2 KHz
Number of
segment driver
61
80
Number of
common driver
16
1/16, 1/32
0
duty cycle
Table 1
Product Name
Table 2
Ordering information
PRODUCT TYPE
DESCRIPTION
LQFP100 Pb-free package.
QFP100 Pb-free package.
LQFP100 general package.
QFP100 general package.
tested die.
LQFP100 Pb-free package.
QFP100 Pb-free package.
LQFP100 general package.
QFP100 general package.
tested die.
LQFP100 Pb-free package.
QFP100 Pb-free package.
LQFP100 general package.
QFP100 general package.
tested die.
LQFP100 Pb-free package.
QFP100 Pb-free package.
LQFP100 general package.
QFP100 general package.
tested die.
SBN1661G_M18-LQFPG
SBN1661G_M18-QFPG
SBN1661G_M18-LQFP
SBN1661G_M18-QFP
SBN1661G_M18-D
SBN1661G_M02-LQFPG
SBN1661G_M02-QFPG
SBN1661G_M02-LQFP
SBN1661G_M02-QFP
SBN1661G_M02-D
SBN0080G_S18-LQFPG
SBN0080G_S18-QFPG
SBN0080G_S18-LQFP
SBN0080G_S18-QFP
SBN0080G_S18-D
SBN0080G_S02-LQFPG
SBN0080G_S02-QFPG
SBN0080G_S02-LQFP
SBN0080G_S02-QFP
SBN0080G_S02-D
2006 Aug 16
4 of 52
data sheet (v6.3)
Avant Electronics
SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02
Dot-matrix STN LCD Driver with 32-row x 80-column
2
2.1
FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION
Funtional block diagram (SBN1661G_M18, SBN1661G_M02)
COM15
SEG60
SEG59
COM1
COM0
SEG1
OSC2(CL)
V5
V4
V3
V2
V1
High Voltage Circuit
Output Driver
Level Shifter
MUX
Display
Control
Time Gen.
COMMON Counter
Mapping Circuit
C/S Mappig Register
Display ON/OFF Register
Display Start Line Register
Page Address Register
Column Address Register
Status Register
Duty Select Register
Static Drive ON/OFF
Register
Line Address
Decoder
Display Data RAM Buffer
32 row x 80 column
(2560 bits)
Display Data RAM
Column Address Decoder
Command
Decoder
Display Data RAM Access Control
Display
Control
Display Data
Read/Write
Control
Microcontroller
Interface
OSC and
Timing Gen.
OSC1(CS)
DB0~DB7
R/W(WR)
RESET/IF
E/RD
M/S
C/D
FR
Fig.1 Functional Block Diagram
2006 Aug 16
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SEG0
data sheet (v6.3)
NXP MCU
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