SN74LS164
Serial-In Parallel-Out
Shift Register
The SN74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift
Register. Serial data is entered through a 2-Input AND gate
synchronous with the LOW to HIGH transition of the clock. The
device features an asynchronous Master Reset which clears the
register setting all outputs LOW independent of the clock. It utilizes
the Schottky diode clamped process to achieve high speeds and is fully
compatible with all ON Semiconductor TTL products.
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Typical Shift Frequency of 35 MHz
Asynchronous Master Reset
Gated Serial Data Input
Fully Synchronous Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
14
LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
1
PLASTIC
N SUFFIX
CASE 646
14
1
SOIC
D SUFFIX
CASE 751A
ORDERING INFORMATION
Device
SN74LS164N
SN74LS164D
Package
14 Pin DIP
14 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS164/D
SN74LS164
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
14
Q
7
13
Q
6
12
Q
5
11
Q
4
10
MR
9
CP
8
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
A
2
B
3
Q
0
4
Q
1
5
Q
2
6
Q
3
7
GND
LOADING
(Note a)
PIN NAMES
A, B
CP
MR
Q
0
– Q
7
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1
2
8
A
LS164
B
8-BIT SHIFT REGISTER
CP
MR Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
9
3 4
5
6 10 11 12 13
V
CC
= PIN 14
GND = PIN 7
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SN74LS164
LOGIC DIAGRAM
1
2
A
D
B
C
D
C
D
C
D
C
D
C
D
C
D
C
D
C
D
CP
MR
V
CC
= PIN 14
GND = PIN 7
= PIN NUMBERS
Q
0
3
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
8
9
Q
1
4
Q
2
5
Q
3
6
Q
4
10
Q
5
11
Q
6
12
Q
7
13
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A or B);
either of these inputs can be used as an active HIGH Enable
for data entry through the other input. An unused input must
be tied HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the logical
AND of the two data inputs (A•B) that existed before the
rising clock edge. A LOW level on the Master Reset (MR)
input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
MODE SELECT — TRUTH TABLE
OPERATING
MODE
Reset (Clear)
Shift
INPUTS
MR
L
H
H
H
H
A
X
I
I
h
h
B
X
I
h
I
h
OUTPUTS
Q
0
L
L
L
L
H
Q
1
–Q
7
L–L
q
0
– q
6
q
0
– q
6
q
0
– q
6
q
0
– q
6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don’t Care
q
n
= Lower case letters indicate the state of the referenced input or output one
q
n
=
set-up time prior to the LOW to HIGH clock transition.
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SN74LS164
DC CHARACTERISTICS OVER OPERATING
TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
–100
27
0.5
20
V
µA
mA
mA
mA
mA
I
OL
= 8.0 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IH
or V
IL
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PHL
t
PLH
t
PHL
Parameter
Maximum Clock Frequency
Propagation Delay
MR to Output Q
Propagation Delay
Clock to Output Q
Min
25
Typ
36
24
17
21
36
27
32
Max
Unit
MHz
ns
ns
V
CC
= 5.0 V
C
L
= 15 pF
F
Test Conditions
AC SETUP REQUIREMENTS
(T
A
= 25°C)
Limits
Symbol
t
W
t
s
t
h
t
rec
Parameter
CP, MR Pulse Width
Data Setup Time
Data Hold Time
MR to Clock Recovery Time
Min
20
15
5.0
20
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5 0 V
5.0
Test Conditions
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4
SN74LS164
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
I
/f
max
MR
1.3 V
1.3 V
CP
t
W
1.3 V
t
PHL
1.3 V
t
W
1.3 V
t
rec
1.3 V
t
PLH
1.3 V
CP
t
PHL
Q
1.3 V
CONDITIONS: MR = H
Q
1.3 V
Figure 1. Clock to Output Delays
and Clock Pulse Width
Figure 2. Master Reset Pulse Width,
Master Reset to Output Delay and
Master Reset to Clock Recovery Time
1/f
max
t
W
CP
1.3 V
t
s
(H)
D
*
1.3 V
1.3 V
1.3 V
t
s
(L)
1.3 V
1.3 V
t
h
(H)
1.3 V
t
h
(L)
1.3 V
Q
1.3 V
1.3 V
Figure 3. Data Setup and Hold Times
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