SN74LS165
8-Bit Parallel-to-Serial
Shift Register
The SN74LS165 is an 8-bit parallel load or serial-in register with
complementary outputs available from the last stage. Parallel inputing
occurs asynchronously when the Parallel Load (PL) input is LOW.
With PL HIGH, serial shifting occurs on the rising edge of the clock;
new data enters via the Serial Data (DS) input. The 2-input OR clock
can be used to combine two independent clock sources, or one input
can act as an active LOW clock enable.
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
16
1
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LOW
POWER
SCHOTTKY
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS165N
SN74LS165D
Package
16 Pin DIP
16 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS165/D
SN74LS165
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
CP
2
15
P
3
14
P
2
13
P
1
12
P
0
11
DS
10
Q
7
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
PL
2
CP
1
3
P
4
4
P
5
5
P
6
6
P
7
7
Q
7
8
GND
LOADING
(Note a)
PIN NAMES
CP
1
, CP
2
DS
PL
P
0
– P
7
Q
7
Q
7
Clock (LOW–to–HIGH Going Edge) Inputs
Serial Data Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Serial Output from Last State
Complementary Output
HIGH
0.5 U.L.
0.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.75 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1 11 12 13 14 3 4 5 6
PL P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
D
S
Q
7
CP
Q
7
10
2
15
9
7
V
CC
= PIN 16
GND = PIN 8
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2
SN74LS165
LOGIC DIAGRAM
11
12
13
14
3
4
5
6
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
10
D
S
2
CP
1
15
CP
2
1
PL
PRESET
Q
0
S
CP
R C
L
Q
0
PRESET
Q
1
S
CP
R C
L
Q
1
PRESET
S Q
2
CP
R C
L
Q
2
PRESET
S Q
3
CP
R C
L
Q
3
PRESET
Q
4
S
CP
R C
L
Q
4
PRESET
S Q
5
CP
R C
L
Q
5
PRESET
S Q
6
CP
R C
L
Q
6
PRESET
Q
7
S
CP
R C
L
Q
7
9
7
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
For clock operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clock is HIGH. Otherwise, the rising inhibit signal will cause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
TRUTH TABLE
CP
PL
1
L
H
H
H
H
X
L
H
2
X
Q
0
P
0
D
S
Q
0
D
S
Q
0
Q
1
P
1
Q
0
Q
1
Q
0
Q
1
Q
2
P
2
Q
1
Q
2
Q
1
Q
2
Q
3
P
3
Q
2
Q
3
Q
2
Q
3
Q
4
P
4
Q
3
Q
4
Q
3
Q
4
Q
5
P
5
Q
4
Q
5
Q
4
Q
5
Q
6
P
6
Q
5
Q
6
Q
5
Q
6
Q
7
P
7
Q
6
Q
7
Q
6
Q
7
Parallel Entry
Right Shift
No Change
Right Shift
No Change
CONTENTS
RESPONSE
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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3
SN74LS165
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
Input HIGH Current
Other Inputs
PL Input
Other Inputs
PL Input
I
IL
I
OS
I
CC
Input LOW Current
Other Inputs
PL Input
Short Circuit Current (Note 1)
Power Supply Current
– 20
0.5
20
60
0.1
0.3
– 0.4
– 1.2
– 100
36
V
µA
I
OL
= 8.0 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
I
IH
mA
V
CC
= MAX, V
IN
= 7.0 V
mA
mA
mA
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Maximum Input Clock Frequency
Propagation Delay
PL to Output
Propagation Delay
Clock to Output
Propagation Delay
P
7
to Q
7
Propagation Delay
P
7
to Q
7
Min
25
Typ
35
22
22
27
28
14
21
21
16
35
35
40
40
25
30
30
25
Max
Unit
MHz
ns
ns
ns
ns
V
CC
= 5.0 V
C
L
= 15 pF
F
Test Conditions
AC SETUP REQUIREMENTS
(T
A
= 25°C)
Limits
Symbol
t
W
t
W
t
s
t
s
t
s
t
h
t
rec
1
The
Parameter
CP Clock Pulse Width
PL Pulse Width
Parallel Data Setup Time
Serial Data Setup Time
CP
1
to CP
2
Setup Time
1
Hold Time
Recovery Time, PL to CP
Min
25
15
10
20
30
0
45
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
V
CC
= 5.0 V
role of CP
1
and CP
2
in an application may be interchanged.
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4
SN74LS165
DEFINITION OF TERMS:
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative hold time indicates that
the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the PL pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer loaded Data to the Q outputs.
AC WAVEFORMS
CP
1
t
W
t
s
CP
2
1.3 V
t
PHL
Q
7
OR Q
7
1.3 V
1/f
max
t
W
t
PLH
1.3 V
1.3 V
Q
7
OR Q
7
PL 1.3 V
t
PLH
1.3 V
1.3 V
1.3 V
t
PHL
1.3 V
Figure 1.
Figure 2.
P
n
t
s(H)
PL OR CP
1.3 V
t
h(H)
1.3 V
t
s(L)
1.3 V
t
h(L)
1.3 V
PL
1.3 V
t
W
1.3 V
t
rec
1.3 V
CP
Figure 3.
Figure 4.
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